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8.3 BINARY SUBTRACTORS 343

B 2(H) B^H) B 0(H)

J_L
J_L
JL
n n n -A/S(H)
W A 2(H) \ J A,(H) \ J A 0(H)
1 1 I
B / B / B A
^ ^
FA,
FA 2 FA 0
i — C Gout g c ifl C C «-J
out c <v c in out - in
o
Add
S n(H) S M(H) S 2(H) S^H) S 0(H)
"— Sign bit if subtraction
FIGURE 8.9
An n-bit adder/subtractor with ripple/carry implemented with full adders and XOR gates.

that if only subtraction is required, the XOR gates can be replaced by inverters. Remem-
ber, if the subtraction results in a negative number, that number is in 2's complement (see
Algorithm 2.9).

8.3.2 Sign-Bit Error Detection

In Subsection 2.6.2 it is stated that the decimal range of representation for n integer bits in
2's complement is

71 1
1
-(r"- ) < #10 < (r ' - 1) for r = 2.
Table 2.7 illustrates this fact with a few examples in 8-bit binary, where the sign bit is the
MSB. What this means with regard to 2's complement arithmetic is as follows: If any two
!
positive numbers sum to a decimal value N\Q > (2"~ — 1), the sign bit will be in error (thus
7 1
negative). Similarly, if any two negative numbers sum to a decimal value N\Q < —(2' " ),
the sign bit will again be in error (thus positive). If number A is positive and number B
is negative, the sign bit will always be correct, assuming that both numbers are properly
represented such that S n-\ is the sign bit for each. Now, with reference to Fig. 8.9, two
negative numbers cannot be properly represented in 2's complement, so that leaves two
positive numbers as the only possibility for sign-bit error in this adder/subtractor or in any
ripple-carry adder. Two examples of 8-bit addition of positive numbers are illustrated in
Fig. 8.10. In Fig. 8. lOa the two numbers sum to decimal 128, resulting in a sign-bit overflow
8
error because 128 > (2 ~' — 1) = 127. The sign bit "1" indicates a negative number, which
is an error. In Fig. 8.10b, the two numbers sum to a decimal value of 127, which is within
the acceptable limit, and no sign-bit overflow error occurs.
It is useful to be able to detect a sign-bit overflow error in a ripple-carry adder or
adder/subtractor so that corrective steps can take place. An inspection of Fig. 8.10 and the
truth table for an FA in Fig. 8.2c indicates that a sign-bit overflow error can occur in the