Page 414 - Engineering Digital Design

384 CHAPTER 8 / ARITHMETIC DEVICES AND ARITHMETIC LOGIC UNITS (ALUs)

examples are the texts of Comer, Ercegovac and Lang, Hayes, Katz, Pollard, Sandige,
Tinder, Wakerly, and Yarbrough. The subject of multiple operand addition and the carry-
save adder appears to be covered adequately only in texts by Ercegovac and Lang and by
Tinder. Note that some of the listed devices may or may not be the strength of a text.

[1] D. J. Comer, Digital Logic and State Machine Design, 3rd. ed., Sanders College Publishing, Fort
Worth, TX, 1995.
[2] M. D. Ercegovac and T. Lang, Digital Systems and Hardware/Firmware Algorithms. John Wiley
& Sons, New York, 1985.
[3] J. P Hayes, Introduction to Digital Logic Design. Addison Wesley, Reading, MA, 1993.
[4] R. H. Katz, Contemporary Logic Design. Benjamin/Commings Publishing, Redwood City, CA,
1994.
[5] L. H. Pollard, Computer Design and Architecture. Prentice Hall, Englewood Cliffs, NJ, 1990.
[6] R. S. Sandige, Modern Digital Design. McGraw-Hill, New York, 1990.
[7] R. F. Tinder, Digital Engineering Design: A Modern Approach. Prentice-Hall, Englewood Cliffs,
NJ, 1991.
[8] J. F. Wakerly, Digital Design Principles and Practices, 2nd ed., Prentice-Hall, Englewood Cliffs,
NJ, 1994.
[9] J. M. Yarbrough, Digital Logic Applications and Design. West Publishing Co., Minneapolis/St.
Paul, 1997.

A few books adequately cover combinational multipliers. These include the texts by
Ercegovac and Lang, Katz, Pollard, and Tinder, all previously cited. Of these, only the text
by Tinder appears to cover combinational dividers.
A somewhat older text by Kostopoulos covers a rather broad range of subjects relative
to arithmetic methods and circuits, including a good treatment of combinational multipliers
and dividers. A recent text by Parhami provides an exhaustive treatment of the subject and
is highly recommended.

[10] G. K. Kostopoulos, Digital Engineering. John Wiley & Sons, New York, 1975.
[11] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press,
New York, 2000.

The subject of arithmetic and logic units (ALUs) is somewhat esoteric. Nevertheless,
it is covered to one extent or another by a few well-known texts. These include those by
Ercegovac and Lang, Hayes, Katz, Tinder, and Yarbrough, all previously cited. In addition,
the text of Mead and Conway discusses an ALU suitable for processor application that is
the starting point for the ALU treated in Subsection 8.8.2 of this text. Apparently, only the
text by Tinder develops the dedicated multilevel ALU by using XOR/SOP logic. Coverage
of dual-rail arithmetic systems, particularly ALUs, is difficult if not impossible to find in
any text. The source on which this text is based is the thesis of Amar cited next. Here,
dual-rail ALUs, multipliers, and dividers, all with completion signals, are discussed in
detail.

[12] A. Amar, "ALUs, Multipliers and Dividers with Completion Signals," M.S. Thesis. School of
Electrical Engineering and Computer Science, Washington State University, Pullman, WA, 1994.
[13] C. Mead and L. Conway, Introduction to VLSI Systems. Addison-Wesley, Reading, MA, 1980.