Page 412 - Engineering Digital Design

382 CHAPTER 8 / ARITHMETIC DEVICES AND ARITHMETIC LOGIC UNITS (ALUs)

G3: nand2 port map (a, b, im2);
G4: nand2 port map (iml, ci, im3);
G5: nand2 port map (im2, im3, co);
end full_adder_example;
— Declare dataflow:
architecture dataflow of full_adder_example is
begin
s <= a xor b xor ci after 12 ns;
co <= (a and b) after 10 ns or (iml and ci) after 16 ns;
-- 16 ns is worst case delay
end dataflow;

-- Declare behavior:
architecture behavior of fulLadder_example is
begin
process (a, b, ci)
variable a, b, ci, s: integer;
begin
if a = '0' then a := 0; else a := 1; — converts a to integer
end if
if b = '0' then b := 0; else b := 1; — converts b to integer
end if
if ci = '0' then ci = 0; else ci := 1; -- converts ci to integer
s:=a + b + ci; -- computes sum of inputs
case s is
whenO=> s <= '0'; co <= '0';
when 1 => s <= T; co <= '0';
when 2 => s <= '0'; co <= T;
when 3 => s <= T; co <= T;
end case;
end process;
end full_adder_example;

In the full adder example just given, notice that all keywords are presented in bold type
and that the symbol "=>" is read as "is the value of." Also note that the operators that
are used are those listed in Fig. 6.44 of Section 6.10 and that the double dash "--" is used
to indicate the beginning of a comment. The delay times given for s and co are based on
average gate path delays of 6 ns for the XOR gate and 5 ns for the two-input NAND gate,
as expressed in Eq. (6.1).
An important feature of VHDL is its modularity capability, which allows models to be
reused in the description of other larger entities. A good example is the VHDL structural