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8.10 VHDL DESCRIPTION OF ARITHMETIC DEVICES                         383


                 description of a four-bit adder composed of four full adders described in the previous
                  example. If Fig. 8.49 is used with reference to Figs. 8.4 and 8.5, the structure of the four-bit
                  adder is given as follows:

                  entity four_bit_adder is
                      port (aO, al, a2, a3, bO, bl, b2, b3, ci: in bit; sO, si, s2, s3, co: out bit;
                 end four_bit_adder;
                 architecture connectJour of four_bit_adder is
                      component fulLadder
                           port (a, b, ci: in bit; s, co: out bit);
                      end component;
                 for all: fulLadder use entity fulLadder_example;
                 signal cl,c2, c3: bit
                 begin
                      FAO: fulLadder port map (aO, bO, ci, sO, cl);
                      FA1: fulLadder port map (al, bl, cl, si, c2);
                      FA2: fulLadder port map (a2, b2, c2, s2, c3);
                      FA3: fulLadder port map (a3, b3, c3, s3, co);
                 end connect_four;
                 end four_bit_adder;

                    Just given is an architectural description for the full-adder primitive, followed by that for
                 a four-bit adder formed by cascading four full-adder primitives. However, within VHDL
                 compilers, encapsulations of such primitives are provided so that they can be easily re-
                 trieved and used in the architectural descriptions of larger systems. Thus, for well-known
                 primitives like those just considered, there is no need to construct the detailed architec-
                 tural descriptions — this has already been accomplished for the convenience of the user.
                 These primitives exist within standard logic packages. The IEEE 1164 standard library is
                 an example, and its contents are made available by making the statements

                                              library ieee
                                              use std_logic_1164.all

                 Once a standard library is made available in the design description, use can be made of data
                 types, functions, and operators provided by that standard. Standard data types include bit,
                 bit-vector, integer, time, and others, and the operators are of the type given in Fig. 6.44.
                 The standard package defined by the IEEE 1076 standard includes declarations for all the
                  standard data types. For detailed information on these and other subjects related to standard
                 libraries and packages the reader is referred to Further Reading.



                  FURTHER READING

                 Most recent texts give a fair account of the basic arithmetic devices, including the full
                 adder, parallel adders, subtractors, adder/subtractors, and carry look-ahead adders. Typical
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