Page 586 - Engineering Digital Design

556 CHAPTER 11 /SYNCHRONOUS FSM DESIGN CONSIDERATIONS

timing diagram, the four BCD code bits will appear in reverse order since they
are introduced LSB first.)
(d) Verify the timing diagram of part (c) by simulating the logic circuit of part (a).
11.11 A 3-bit serial odd-parity detector is to be designed that will issue an active output
pulse PoddDet(L) any time a series of three clock periods samples an odd number
of active pulses (one or three, in any order) on an input pulse string X. The output
must be issued only when clock is active.
(a) Construct an optimum state diagram and state table for this detector. To do
this, make effective use of the "from rule" discussed in Subsection 11.10.2
and initialize into the 000 state to begin the process. Remember that the
FSM must issue an output on the active portion of the clock waveform.
(Hint: This is a Mealy machine of five, six, or seven states depending on the
design.)
(b) Design the logic circuit for this detector by using three FET JK flip-flops and
a gate-minimum NS and output logic. To do this consider using XOR patterns
where appropriate. Assume that X arrives active high from a mechanical
switch, and that it must be debounced and synchronized antiphase to the clock
triggering edge. Show all input conditioning circuitry and their connections
to the FSM. Plan to use a SPOT debouncing circuit of the type shown in
Fig. 11.32a. [Hint: If Part (a) is done correctly, two to four gates will be
required for the NS and output logic.]
11.12 An FSM is to be designed that will issue an output according to the following
requirements:

If clock samples S active with both X and Y inactive, then Z is issued on
Y following XY or X following XY, provided that these events are spaced
one clock period apart. If these conditions are not met (an EQV condition),
then Z will not be issued, and the FSM must wait for S to be sampled
inactive before the FSM can return to the initial state and start the process
over again. The output Z must be issued for only one clock period, after
which the FSM must return unconditionally to the initial state.

Construct a state diagram and state table for this FSM and give it a glitch-free state
code assignment. Plan to initialize the FSM into the 000 state. (Hint: Properly
done, the state diagram will have only six states.)
11.13 Shown in Fig. PI 1.6 is a state diagram for an FSM that has two inputs, X and Y,
and one output, Z.
(a) Given the state code assignment indicated, use the array algebraic approach
to obtain the NS expressions for this FSM. To do this, first construct the
state table to obtain the state matrix S and destination matrix D. Then find
the function matrix F Ns and the next matrix NS by following the exam-
ple in Section 11.11. End with an optimum set of logic equations for DA
and D B.
(b) Repeat the array algebraic approach to obtain the output function for Z.