Page 644 - Engineering Digital Design

614 CHAPTER 13/ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES

2. Memory. Choose from the following:

Discrete flip-flops (D, JK, or T that are edge-triggered or master/slave)
Shift registers
Counters

3. Registered PLDs for total state machine design. Choose from the following:

R- and V-type PALs
FPGAs (e.g., Actel and Xilinx)
GALs, EPLDs, PLSs, etc. (see Subsection 7.7.4 for definitions)

4. Input and output conditioning circuits. Choose from the following:

Synchronizers
Synchronizer/stretchers
Debouncing circuits
Output holding (storage) registers for filtering

5. Initialization and reset circuits. Choose from the following:

Sanity circuits

The preceding list of components may not be exhaustive, but it covers most of the
components that are commonly used in modern state machine and system-level design.
Clearly, the choice of components depends on various considerations, including intended
use, physical realization, programmability, and a host of other factors. For example, if it is
the intent of the designer to place the state machine on chip, the choice is somewhat limited.
In this case, a proper choice might include the use of a PLA and discrete flip-flops chosen
from categories 1 and 2, together with the appropriate input and output conditioning circuits
and initialization circuit. On the other hand, if the choice is off chip, many more alternatives
are available, mainly because of the vast numbers of possibilities contained in categories 1,
2, and 3, perhaps limited only by the imagination of the designer. In the following sections,
several exemplary design architectures are demonstrated in the design of various FSMs and
controlled systems. Before proceeding it is recommended that the reader review the design
procedure laid out in Subsection 11.9.1.

13.2 ARCHITECTURES CENTERED AROUND NONREGISTERED PLDs

The model used for designs centered around nonregistered PLDs is shown in Fig. 13.1,
together with block symbols representing possible input and output conditioning circuits.
This model is sometimes referred to as the Huffman model. The PLD represents a ROM, a
PLA, or a basic I/O PAL and is used to generate both the NS- and output-forming logic. The
memory can be any of the devices listed previously in category 2, namely discrete flip-flops