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14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS 705

1. Altering the branching path without changing the basic algorithm of the FSM.
2. Changing the state code assignment to remove all race conditions or move the race
condition elsewhere in the state diagram without creating any new timing defects.
3. Adding a buffer (fly) state to remove the race condition without violating critical
timing constraints.
4. Adding additional state variables.

The action of removing the critical race by moving the causal race condition elsewhere in
the state diagram is complicated by the possible formation of ORGs. Not only must the
change be scrutinized as to the formation of another critical race, but the formation of static
hazards and ORGs (not originally present) must be considered. The issue of static hazards
in the NS-forming logic will be considered next. Obviously, the safest course of action in
removing a critical race is to change the state code assignment so as to eliminate all race
conditions in the FSM. Doing so, eliminates all race-related timing defects automatically.

14.10.3 Static Hazards in the NS and Output Functions

Before proceeding with this subsection, the reader should review Sections 9.2 and 11.3
dealing with static hazards (s-hazards) in combinational circuits and in the output of syn-
chronous FSMs, respectively. In Section 11.3, the treatment of s-hazards in the NS-forming
logic was not an issue since all such timing defects are filtered out by the memory flip-flops.
Of course, asynchronous FSMs have no such filtering mechanism and are therefore subject
to the problems that hazards can create in the NS-forming logic. Whereas s-hazards in the
output-forming logic of asynchronous FSMs cannot cause the parent FSM to malfunction,
s-hazards in the NS-forming logic can and do cause FSMs to malfunction. This may be
viewed as yet another complicating timing defect that distinguishes the asynchronous FSM
from its cousin, the synchronous state machine.
Static hazards in both the NS and output forming logic of asynchronous FSMs fall
into two general categories: externally initiated and internally initiated static hazards, as
illustrated in Fig. 11.8 for s-hazards in the output logic of synchronous FSMs. In fact,
there is little difference in the methods used for detection and elimination of s-hazards in
asynchronous and those used for s-hazards in the output functions of synchronous FSMs.
It is important for the reader to remember the following:

Any suspect hazardous transition found by analyzing the NS and output functions of
an asynchronous FSM must be verified by inspection of the state diagram — this is
standard operating procedure for s-hazard analysis in such state machines.

Since s-hazards in the output-forming logic cannot cause malfunction of the asynchronous
FSM itself, attention in this subsection will be devoted to these timing defects in the NS
forming logic. The analysis of static hazards in the output logic of asynchronous FSMs
follows closely developments in Section 9.2 and in Subsection 11.3.1.
As the first and simple example, the transparent D latch, discussed in Subsection 10.7.1,
will be designed by using the LPD model and then analyzed for an s-hazard timing problem.
Shown in Fig. 14.21a is the state diagram for the D latch reproduced from Fig. 10.24a.
By using the mapping algorithm in Section 10.6 to combine the excitation table for the