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14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS 711

it is only the delay through an inverter that is the causal effect, there is the possibility
that the FSM will function properly even without hazard cover. But since this cannot be
assured, hazard cover must be added. Again, this should be considered as standard operating
procedure in dealing with static hazards in the NS logic as well as the output logic.

14.10.4 Essential Hazards in Asynchronous FSMs
Elimination of all endless cycles, critical races and static hazards from an asynchronous FSM
operated in the fundamental mode does not ensure proper operation of the FSM. Certain
noncombinational hazards produced by explicitly located asymmetric path delays in gates
and/or on leads are guaranteed to cause such FSMs to malfunction. These hazards, called
essential hazards (E-hazards), are steady-state sequential hazards in the sense that they
involve the change of two or more state variables in otherwise steady-state output signals.
The term "essential" does not imply "needed" or "necessary," but rather, refers to the
fundamental mode of FSM operation. Without exception, E-hazards cannot be eliminated
by adding redundant cover as can s-hazards.

General Requirements for E-hazard Formation The general requirements that must
be met before an E-hazard can form are as follows:

1 . The asynchronous FSM must operate in the fundamental mode.
2. There must be at least two state (feedback) variables — hence, at least three states —
and at least one external input, designated as the initiator input.
3. There must be at least two paths of propagation of the initiator to the first invariant
state variable: one path directly to the first invariant and at least one other indirect
path to the first invariant via the second invariant state variable. Both the initiator and
second invariant must meet at a specific gate called the race gate.
4. An asymmetric path delay must be explicitly located in the direct path of the initiator
to the first invariant state variable and must be at least of the minimum magnitude to
cause the E-hazard to form.

The process of E-hazard formation involves a "critical" race (to the race gate) between
the initiator and the second invariant state variable. If the race is won by the second invariant,
an E-hazard is formed. An explicitly located path delay of sufficient duration will ensure
that the race is won by the second invariant state variable and, consequently, cause the
E-hazard to form.
The path delay requirements for the formation of a first-order E-hazard in a two-level
NS logic system are given in Fig. 14.26. Here, two race gate (RG) types are identified. For
the case of the first-level race gate in Fig. 14.26a, the path delay requirement for E-hazard
formation is given by

Ti+T 2 , (14.16)

and for the second-level race gate in Fig. 14.26b by

(Af £ +Ti) > T 2 + T 3 + T 4. (14.17)