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2.4 SOC Design Challenge
Since an SOC integrates multiple chips of a system onto a single chip, it is targeted to a
specific application domain. While the SOC addresses the application requirements in
a better way (in terms of cost, power, form factor, and other considerations), building an
SOC involves a significant investment, so it’s important to understand business
considerations that challenge the SOC design process.
Building a complex SOC in an advanced CMOS process typically requires a
development cost of more than US$10 million and a cycle time from design start to
ready for production of 18+ months. Assuming a 40 percent gross profit margin (GPM),
the SOC revenue needs to cross US$25 million to reach break-even, which means that
the target available market needs to be in excess of US$75 million to US$100 million.
Given that not many such applications exist, the SOC design needs to address the
problem of accelerating and maximizing the return on investment, and also being able
to address markets with smaller revenue potential. This implies a focus on
• Reducing cycle time
• Reducing development cost (reduced effort)
• Providing differentiation to command a higher GPM
• Reducing the cost of build (COB)

The SOC design challenge is thus an optimization problem along the following
vectors:

• Cost (die cost, test cost, package cost)
• Power dissipation (leakage, dynamic)
• Performance (must meet real-time constraints)
• Testability
• DPPM, reliability, yield
• Application-specific requirements—EMI, SER, etc.
• Design effort and cycle time
The conflicting nature of these requirements implies the need to drive appropriate
trade-offs. The decisions taken at the SOC definition phase have the highest impact on
the optimization parameters. The design effort and cycle time are driven primarily by
the chip create phase. The SOC design challenge is hence addressed via a two-phase
approach, where in phase I—the SOC definition phase—the microarchitecture-level
decisions are taken to meet the key product parameter goals such as die size, power
dissipation, and performance. In phase II—the SOC create phase—a platform-based
design approach is adopted to reduce the design effort and cycle time. In the following
sections we highlight the SOC design challenges in both these phases.

2.4.1 SOC Design Phase 1—SOC Definition and Challenges
As discussed earlier, the customer requirements of cost, power, performance, and form
factor apply to the entire system as against the chip alone. The SOC definition phase