Page 74 - System on Package_ Miniaturization of the Entire System

Intr oduction to System-on-Chip (SOC) 51

HW/SW SW Dev and
applications debug tools

Product
engineering SOC Design Packaging

Soft and Silicon
EDA tools/
design flows hard IP technology
create development

FIGURE 2.9 Concurrent engineering.

hence needs to comprehend system-level implications of the SOC microarchitecture-level
decisions. In most cases the SOC and the system are developed in parallel, thus posing
concurrent engineering challenges. These challenges if addressed can provide
opportunities to drive optimal system definition. Figure 2.9 shows multiple concurrent
engineering challenges.
For most DSP applications, real-time performance is a critical system requirement.
The system performance is typically determined by the SOC microarchitecture along
with the software running on the embedded processor. The SOC definition phase hence
involves working closely with the software applications team to profile the code,
identify performance bottlenecks, and drive appropriate hardware-software partitioning
decisions.
The amount of software running on the embedded processor(s) of an SOC has been
increasing over the years. The criticality of a user-friendly application development
environment has consequently gone up. An SOC hence needs to provide appropriate
hooks in the hardware to enable the software debug. Debug architecture is an important
component of an SOC microarchitecture, and it is best defined jointly with the team
developing the application development environment for the SOC.
Time-to-market is a big concern for most customers, especially in the consumer
electronics space. It’s not adequate to build functional silicon; it needs to be followed by
product engineering functions that get it ready for volume production. The SOC design
team works closely with the product engineering team starting from the SOC definition
phase to build appropriate hooks in the SOC microarchitecture and provide necessary
information to be able to get the test programs ready just in time for the silicon, thus
enabling rapid ramp to volume production.
Electronic design automation (EDA) is a critical enabler to meet the aggressive cycle
time goals. Since with each generation the design complexity keeps going up significantly,
in many cases the design flow automation and the design methodology gets built con-
currently with the chip create process.