Page 77 - System on Package_ Miniaturization of the Entire System

54 Cha pte r T w o

Application Algorithm
Security systems 4*CIF MPEG4 encode/decode
IP Videophone H.263 encode
Video servers Multichannel MPEG2 encode/stream media
encode
PVR/home server MPEG2 encode/decode
IP set-top box/streaming media decode Streaming media decode
TABLE 2.1 Target Applications and Algorithms for DM642

It can be noted that for an application, there can be multiple solutions possible
that meet performance requirements and balance the CPU, memory, and I/O
bandwidth. The most optimal solution is then decided based on the cost and power
dissipation goal. For example, a smaller L1P can reduce the die size; however, because
of an increased number of cache misses, it may require that the CPU be run at a higher
clock rate, which in turn would require the chip to operate at a higher voltage resulting
in increased power dissipation. In case of video processing applications, which are
data intensive, the size of L2 can impact the EMIF bandwidth requirement. While a
smaller L2 implies a lower chip cost, increasing the EMIF clock rate, for example,
from 100 to 133 MHz may result in a cost increase at the system level due to an increase
in the cost of the off-chip memory that needs to run at a higher data rate. In general
for the same application throughput different L2 sizes can result in an EMIF bandwidth
ranging from say 32 bits at 100 MHz to 64 bits at 133 MHz. Since 64-bit I/O switching
results in increased noise (package implications) and higher power dissipation, the
decision on the memory subsystem needs to be driven by the desired cost-power
tradeoff.

Chip-Package Codesign
Since the package is an important contributor to the cost, power dissipation, and
performance of an SOC, in this section we discuss chip-package codesign to optimize
system-level objectives. The performance (megahertz) of a chip is dependent on the
resistive drop, which in turn is dependent on the package. A flip-chip package
provides a lower IR drop than a wire-bond package, and hence supports higher
performance.
A flip-chip package, however, is significantly more expensive than a wire-bond
package (Figure 2.11). It is, however, possible to limit the cost overhead by using a low-
cost flip-chip package.
The flip-chip package cost is driven by the number of layers, standard substrates
versus built-up substrates that enable micro-vias (Figure 2.12), substrate size, bump
pitch, and other factors. The package selection from a pin-out point of view is a tradeoff
between the package cost (substrate size), form factor, and board-level cost. While a
smaller ball pitch translates to a smaller package size, the board-level manufacturability