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Simulation/Verification
Executable System- HW/SW Functional/ RTL/ISS HW Gate-level/SPICE
Spec. Level Cosimulation Behavioral -SW Cosimulation HW-SW Cosimulation
-SW Cosimulation
Custom logic C assembly/ coding
SW requirements SW architecture SW integration Compile code for target processor Verification Profiling and optimization Regression
Reusable modules Subsystem integration
Requirements & Specifications System architecture design HW/SW partitioning & tradeoffs IP Respository SW HW Processor/ Application DSP cores specific Memories module Peripherals in C/ Controllers assembly Drivers Bridges Functional verification Subsystem-level Chip-level Tech libraries Simulation Synthesis Formal verification D
Reusable modules Subsystem Integration PG
Design constraints HW requirements HW architecture Chip-level integration STA (Wire load) Floorplanning FVEC (Gates-Gates) SDF Generation /STA VEC (Gates-Gates) SDF Generation/STA SOC HW-SW codesign methodology.
Custom logic RTL Coding Functional simulation Synthesis FVEC (RTL-Gates) Place & GRoute CTS & DRoute Regression
ATPG
DFT
FIGURE 2.13
F e e d b a c k
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