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60 Cha pte r T w o

consortium that was launched at the Design Automation Conference 2004 was the
Structure for Packaging, Integrating, and Re-using IP with Tool-flows (SPIRIT) to cover
a Register Transfer Level (RTL) encapsulation for automated IP integration and
interoperability of IP with multiple toolsets. This included tools for system-level design,
verification, and simulation as well as synthesis.
IP cores or blocks can be integrated in three variants on an SOC:
• Hard. These blocks are physical design completed and optimized at a particular
process node. As a result, while these blocks can differentiate in terms of speed,
power, and area, they are the least flexible and portable across technology nodes
and SOC designs, given that their physical attributes such as size and aspect-
ratio cannot change.
• Soft. These blocks are reused as a register transfer–level representation of the IP
along with the necessary synthesizable constraints and test benches to
implement and verify these blocks in the SOC context. In contrast to hard
blocks, these IP components have the most flexibility and portability across
SOC designs and are amenable to in-context physical optimization for best SOC
power-speed-area parameters.
• Firm. This type of IP reuse combines the best advantages of both the above two
reuse scenarios where the IP is optimized for power-speed-area careabouts
across process nodes. However, given that the physical layout is uncommitted,
the IP is configurable to various “use” scenarios.

As evident from these IP reuse variants, the right SOC-level tradeoffs in terms of
time-to-market, performance requirements, and portability need to be made in deciding
the reuse strategy.
An important development in the area of IP reuse for SOC designs is the concept of
platform-based design. This has evinced significant debates and analysis on the
advantages and challenges it brings. A platform-based SOC design is based on the
fundamental premise that if you have an architecture, a bunch of predefined building
blocks, including a processor or a DSP, a standard bus, memory controller, and SW
tools, it would be very easy to quickly generate several derivative chips targeted at the
application segment. Needless to say, this enables rapid SOC development and time-to-
market that several market segments demand. For example, cell phone and automobile
manufacturers can very easily deploy a platform-based development model to spin
incremental variants of their models into the market without having to design each chip
from scratch. A direct benefit of this approach of working at the system level is that it
promotes a lot more architectural-level analysis and tradeoffs during SOC design and
brings into focus a system-level view to SOC design and verification. A critical benefit
of a platform-based SOC development is reduced risk. Given the huge mask costs
outlined above in the 90-nm or 45-nm process nodes, any design mistake will result
in a costly respin as well as a delay in the product getting to the market by more than
6 months. This is where the SW codevelopment model of the SOC brings in the benefit
of end customers being able to simulate their application code on the system even
before the SOC design can be sent for fabrication. A platform-based approach therefore
allows for such HW-SW concurrent design with SW being ready before silicon, thereby
also reducing SW development cycle times. Table 2.2 provides an example of how a
platform-based design at 90 nm helps reduce several SOC development cost and time-
to-market parameters. In some sense, the “realm” of reuse in a platform-based approach