Page 83 - System on Package_ Miniaturization of the Entire System

Intr oduction to System-on-Chip (SOC) 59

The system-level design process typically starts with a description of the system to
be built in terms of requirements mainly driven by the applications’ “use” context and
then translates to capturing the functional aspects of the system in terms of the behavior.
The next step is to define the system architecture that primarily involves coming up
with the required hardware platform and the partitioning of the system into hardware
and software components. This is a very critical phase of system design and has to be
accomplished in the context of the constraints involved such as performance, cost, and
power. Correct tradeoffs at this stage are absolutely essential to address the overall SOC
requirements to meet the customer’s product specification. The HW requirements are
then translated into a SOC design architecture specification that is typically then
described in hardware description languages (HDL) like VHDL or Verilog. The cor-
rectness of the specification is verified using simulation tools that verify the functionality
of the implemented HW. The HDL description of the HW is then synthesized to a target
technology library followed by the physical implementation of the design into mask
layers. At every stage of the HW design flow, care is taken using functional equivalence
checker tools that the functionality is not changed by downstream logic and physical
synthesis and implementation tools. The SW components are typically coded in high-
level programming languages such as C/C++ or even assembly level and then simulated
for correctness. The key aspect in getting both the HW and SW components, and hence
the overall system right, is cosimulation of the HW and SW. This is typically performed
using either HW acceleration systems or in-circuit emulation that can co-verify the HW
along with the embedded SW components.
SOC Integration
As indicated earlier, just as CMOS scaling drove the PC era for the last two decades,
large-scale integration of digital and analog/RF functionality on a SOC is going to fuel
the Internet era going forward. This is going to pose a significant challenge if we
combine the technology scaling issues outlined in the previous section along with the
sheer complexity of the SOC integration challenge.
One of the most critical components of SOC design is the integration of predeveloped
pieces of functionality called intellectual property (IP). These IP blocks can offer a huge
differentiation to designers building SOC designs for various applications and helps
reduce development cycle-time significantly. However, while attempting to integrate
such multiple IPs, the SOC designer is faced with tremendous challenges in
understanding these predefined functional IPs as well as coping with the issues that
need to be dealt with in getting these IPs to talk to the rest of their SOC and in verifying
the whole system thereafter. Complicating the problem is the reality that IP developers
and SOC designers are geographically distributed across the world. This can, very
often, offset the advantage of reducing development cycle-time that the reuse itself
brings in. Several initiatives have been started in the industry today to tackle this major
IP reuse issue. One such industry consortium called the Virtual Socket Interface Alliance
(VSIA) was founded in September 1996 with an attempt to bring together IP [also called
virtual components (VC) by this consortium] developers and SOC houses to work
together to define standards for design and integration of reusable IP. Several IP-centric
bus definitions and interconnect strategies have been suggested to make IP reuse as
seamless as possible for the SOC designer. A VC quality checklist was also developed
by this consortium to quantify the “readiness” of these components for reuse. This
focused on qualifying an IP from both a developer’s perspective as well as from an
integrator perspective and incorporating as many best practices as possible. Another