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Intr oduction to System-on-Chip (SOC) 57

The preceding considerations in many cases result in conflicting requirements. The
key challenge in chip-package codesign is driving the right tradeoffs. The codesign
methodology requires the following capabilities:
• Die size estimation
• Power estimation
• Physical design methodology—unifying chip, substrate, and potentially board-
level design
• Chip-package-board electrical modeling
• Package thermal modeling
• Cost model to drive appropriate tradeoffs

While the SOC definition phase provides the opportunity to impact area, power, and
performance parameters the most, the SOC design phase aims at achieving maximum
technology entitlement for a given SOC microarchitecture. The design phase not only
has the most impact on cycle time and effort goals, but it’s the phase where reliability
and testability aspects are addressed in support of robustness and DPPM goals.

2.4.2 SOC Design Phase II—SOC Create Process and Challenges
In this section we discuss challenges faced during the chip create phase of SOC design
and also present approaches to address these challenges. We start by first describing the
overall SOC design methodology—specifically the HW-SW codesign aspects. We then
focus on various components of the SOC create process starting with chip integration,
verification, and design for test considerations. While technology scaling enables an
increasing level of integration, it brings with each generation unique design challenges.
We hence present implications of technology scaling and discuss abstraction as a
mechanism to manage increasing chip create complexities. We then present challenges
with the physical design phase of the SOC create process—covering design planning
and design closure. We finally discuss challenges (specifically noise) in monolithic
integration of analog modules with complex digital logic.
SOC HW-SW Codesign and Architectural-level Partitioning
Since an SOC is built using one or more embedded processors, the HW-SW codesign
and verification is an important component of developing an optimal overall solution.
Figure 2.13 shows the flow that starts with HW-SW partitioning, the creation of HW
and SW components, and finally their system-level integration and verification.
Several modern-day applications, particularly embedded applications like
automotive, telecommunications, and consumer electronics, involve both software and
hardware components. The software generally influences the features and flexibility,
whereas the hardware provides the performance. Traditionally, the software and
hardware definitions and descriptions were developed sequentially and very often in
isolation, thereby leading to overall system incompatibilities and in many cases
suboptimal system architecture. This directly impacts time-to-market due to iterations
and rework. To address the growing problems associated with the design of complex
SOC and the need for extensibility and configurability in processor-based design,
electronic system-level (ESL) methods are becoming very common. A typical system-
level design and the components and data flow involved are described in Figure 2.13.