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CMOS Transistor Fabrication 267



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                                                       Saitoh, W. et al: 35 nm metal gate p-type metal oxide semicon-
           12. Compare minimum CMOS inverter area for:  ductor field-effect transistor with PtSi Schottky source/drain
              (a) non-self-aligned Al-gate              on separation by implanted oxygen substrate, Jpn. J. Appl.
              (b) self-aligned polysilicon gate;        Phys., 38 (1999), L629–L631.
              keeping all other factors identical.     Stinson, M. & Osburn, C.M.: Effects of ion implantation on
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                                                        gies, IEEE TED, 38 (1991), 487.
              different metals (optimized for their respective  Wolf, S.: Silicon Processing for the VLSI Era, Vol 2 – Process
              devices), how many process steps would be added  Integration, Lattice Press, 1990.
                             +
                           +
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           REFERENCES AND RELATED READINGS             Yagishita, A. et al: Improvement of threshold voltage deviation
                                                        in damascene metal gate transistors, IEEE TED, 48(8)
           Chesboro, D.G. et al: Overview of gate linewidth control in  (2001), 1604, Figure 25.1.
            the manufacture of CMOS logic chips, IBM J. Res. Dev., 39  IBM J. Res. Dev., 43(3) (1999): special issue on Ultrathin
            (1995), 189.                                dielectric films.
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