Page 317 - Sami Franssila Introduction to Microfabrication

296 Introduction to Microfabrication

HF etching of Pyrex glass with polysilicon mask; MEMS part to the IC part is preferably done by diffu-
silver lift-off metallization; sions because metal–silicon interfaces cannot be made
anodic bonding. until fairly late in the process. Despite its name, this
approach still has some of the MEMS steps to be done
after the completion of IC processing: usually the release
28.6 IC–MEMS INTEGRATION
of freestanding structures and maybe metallization.
The plug-up process shown in Figure 28.10 is an
Silicon is just one possible substrate for MEMS, but
it is the one that promises integration with electronic SOI MEMS–IC process that consists of the following
(e.g., CMOS circuitry) and optical (e.g., photodiodes) main modules:
functions that can be fabricated on the same wafer. 1. MEMS structure processing and encapsulation;
This section discusses some general integration issues 2. CMOS process;
encountered with IC–MEMS integration. 3. MEMS structure release.
There are three main ways of integrating IC and
MEMS devices on a wafer level: There is no topography increase in SOI MEMS
steps, and the sealed cavities do not pose problems for
– MEMS before IC; subsequent CMOS processing if the CMOS and MEMS
– MEMS and CMOS interleaved; parts are side by side on a wafer.
– MEMS post processing. Interleaved fabrication offers the greatest challenges
for process and device designers because there are
All of these have their strengths and weaknesses, but so many trade-offs to be made. Take polysilicon, for
in all cases, process complexity increases and cases of instance: CMOS gate polysilicon is typically 0.25 µm
successful commercialization of monolithic integration thick, whereas micromechanical poly is ca. 2 µm thick.
remain few. Hybrid integration at chip level is still the Gate poly is optimized for poly/SiO 2 interface properties
norm in the industry: MEMS chip and the accompanying and it is highly doped. Micromechanical poly is designed
ASIC (for readout, calibration and self-testing) are for minimal stresses and stress gradients. If two separate
separate chips. This is partly a commercial (production polysilicon depositions are needed, with two different
volume) issue, and partly a technical issue: very few doping/annealing steps, the benefits from integration
advanced IC fabs are capable of MEMS processing. start disappearing.
IC packaging is generic and simple: both plastic and Post-processing of MEMS devices (Table 28.5)
hermetic packages are independent of chip design and includes a great number of choices: micromechanical
technology. With MEMS, it is a wholly different story: structures can be made by both subtractive (etching)
movable structures may stick during the anodic bonding techniques and additive (deposition) techniques.
process, even though sticking might have been avoided
in release etching. Wafer dicing relies on 20 000 rpm saw Table 28.5 MEMS post-processing
blades that might bring MEMS structures to resonance,
water cooling may lead to sticking and silicon dust may Subtractive Notes
block cavities and gaps.
Zero-level package is a structure that seals the MEMS Bulk silicon backside Wet or DRIE, double-side
etching lithography
part from the ambience. It is preferably applied on the
Bulk silicon front side Single sided, wet or
whole wafer, in a manner not unlike passivation nitride
etching plasma
deposition in IC industry. Two routes have been explored:
Surface; front-side Thin-film mechanical
deposition and wafer bonding (see Figure 17.2). The etching elements only
former should have zero step coverage for optimum SOI front/back etching Buried oxide etch stop for
performance, acting as a roof only. The latter has the both, wet or DRIE
disadvantage that an additional wafer is required.
In the MEMS-first approach, MEMS devices are pro- Additive Notes
cessed and covered (e.g., by TEOS), and hopefully, they
will not be adversely affected by the hundreds of pro- Polysilicon/polySiGe Thermal limit on poly
annealing
(LPCVD)
cess steps it takes to complete the IC. IC-process tem- Aluminium (sputtering) Layer thicknesses limited
peratures severely limit the selection of materials for Nickel (electroplating) Thick layers possible
MEMS-first integration: silicon, polysilicon, oxide and Nitride (PECVD) Stress control
nitride are really the only candidates. Connecting the