Page 319 - Sami Franssila Introduction to Microfabrication

298 Introduction to Microfabrication

Another distinction relates to silicon real estate: are 3. If vertical walled through-wafer structures are
the IC and MEMS devices on top of each other, or made, what is the minimum size and space that can
side by side? This has important implications for etch be realized by: (a) DRIE, (b) <110> wet etching
stop, alignment and device packing density. Bulk silicon and (c) <100> wet etching?
removal can also be used to leave n-wells of the 4. The deflection of a circular membrane under pres-
4
CMOS-part intact by electrochemical etch stop, which sure is given by h = 0.666 (r p/Et) 1/3 , where r is
provides thermal isolation (see Figure 28.11). This the radius, t the thickness and E the Young’s mod-
offers improved sensitivity for weak thermal signals. ulus of the diaphragm. What is the deflection that
CMOS wafers can be treated as any other substrates, corresponds to a pressure difference of 25 mtorr?
even though they are very expensive: CMOS wafer cost What is the corresponding capacitance change?
is ca. $500 for a finished 150 mm wafer with 0.8 µm 5. Analyse the fabrication process for the nanoholes
devices on it, versus $20 for a bulk wafer, $50 for an shown in Figure 13.13.
epiwafer and $200 for an SOI wafer. CMOS wafers 6S. What is the thickness of beams and membranes that
as substrates have certain limitations: the maximum you can make with the p ++ etch stop technique if
processing temperature is limited by the silicon–metal diffusion is used to fabricate the p ++ layer?
interface stability. The standard 450 C limit has been 7. Calculate the mask dimensions for both masks
◦
◦
raised to ca. 700 C by utilizing tungsten with diffusion when 100 µm lateral isolation distance is needed
barriers. Usually, the topmost metallization layer is in the thermally isolated structure with silicon heat
not planarized, but CMP is needed when CMOS is equalization mass (Figure 28.3(b)).
used as a substrate. CMOS transistors have to be 8. Calculate the mask dimensions and estimate vertical
protected from chemical contamination. This has been etched depths for the accelerometer shown in
done successfully by combined oxide/nitride passivation Figures 21.10 and 28.7.
and polymeric protective coating, and KOH etching can 9. Design a fabrication process for the 3D silicon
be accomplished without any deleterious effects on the shadow mask shown in Figure 28.8
CMOS. Array devices with CMOS transistor drivers 10. What is the linear density of ink channels of
include digital micromirror devices (DMD), IR pixel technology shown in Figure 28.6?
sensors and fingerprint sensors.

REFERENCES AND RELATED READINGS
28.7 EXERCISES
1. Nozzles are fabricated by etching through a Briand, D. et al: Design and fabrication of high-temperature
380 µm thick <100> silicon wafer anisotropically micro-hotplates for drop-coated gas sensors, Sensors Actua-
(Figure 28.5). A 540 µm wide mask pattern is used. tors, B68 (2000), 223.
(a) Calculate the size of holes produced by an Brugger, J. et al: Self-aligned 3D shadow mask technique
for patterning deeply recessed surfaces of micro-electro-
ideal process. mechanical systems devices, Sensors Actuators, 76 (1999),
(b) Calculate the effect of the following real world 329.
uncertainties: Chen, J. & Wise, K.D.: A high-resolution silicon monolithic
1. Wafer thickness variation: 380 µm ±5 µm; nozzle array for inkjet printing, IEEE TED, 44 (1997), 1401.
2. Total thickness variation TTV of 1 µm; de Boer, M.J. et al: Micromachining of buried micro channels
3. <100>:<111> crystal plane selectivity 33:1 in silicon, J. MEMS, 9 (2000), 94.
versus 30:1; Griss, P. et al: Development of micromachined hollow tips for
4. Mask width +1% narrower than the design protein analysis based on nanoelectrospray ionization mass
value. spectrometry, J. Micromech. Microeng., 12 (2002), 682.
Guenat, O.T. et al: Ion-selective microelectrode array for
2. If a piezoresistive pressure sensor diaphragm is
intracellular detection on chip, Transducers ’03 (2003), p.
made in an epitaxial layer, and diaphragm etching
1063.
is stopped by pn-junction etch stop, how do the
Hierlemann, A. et al: Microfabrication techniques for chemi-
following affect sensor structure: cal/biosensors, Proc. IEEE, 91 (2003), 839; special issue on
(a) wafer thickness; chemical and biological microsensors.
(b) wafer TTV; Kovacs, G.T.A. et al: Bulk micromachining of silicon, Proc.
(c) epitaxial layer thickness. IEEE, 86 (1998), 1543.