Page 24 - MEMS Mechanical Sensors

2.3 Fabrication Techniques 13

cannot be ignored. Thick oxide films can cause bowing of the underlying substrate.
Freestanding oxide membranes will buckle and warp, and thin oxides on silicon
cantilevers will make them curl.

2.3.1.2 Chemical Vapor Deposition
Solid films, such as silicon dioxide, silicon nitride, and amorphous or polycrystal-
line silicon (polysilicon) can be deposited on the surface of a substrate by a CVD
process, the film being formed by the reaction of gaseous species at the surface. The
three most common types of CVD process are low-pressure CVD (LPCVD), plasma
enhanced CVD (PECVD)—in which radio frequency (RF) power is used to generate
a plasma to transfer energy to the reactant gases, and atmospheric pressure CVD
(APCVD). For LPCVD, the step coverage (conformality), uniformity, and the com-
position and stress of the deposited layer are determined by the gases used and the
operating temperature and pressure. For PECVD, the layer properties are affected
additionally by the RF power density, frequency, and duty cycle at which the reactor
is operated; and for APCVD, in which the deposition is mass transport limited, the
design of the reactor is significant.

2.3.1.3 Polysilicon and Amorphous Silicon
Films deposited by LPCVD are used widely in the integrated circuit industry.
Amorphous silicon and polysilicon, in particular, are usually deposited by LPCVD
using silane. Although polysilicon can be deposited by PECVD, this is generally
only done where large deposited areas are required or for thin-film transistor liquid
crystal displays. The properties of LPCVD amorphous silicon and polysilicon lay-
ers depend on the partial pressure of silane in the reactor, the deposition pressure
and temperature, and, if doped in situ, on the gas used for doping. If doped silicon
is required, then diborane, phosphine, or arsine is included in the deposition
process. The deposition temperatures range from 570°C for amorphous silicon to
650°C for polysilicon with the silicon grain size increasing with temperature. The
final grain size for amorphous silicon is usually determined, however, by the tem-
perature at which the film is annealed after deposition. For MEMS devices anneal-
ing can also be used to control the stress in amorphous and polysilicon films. The
residual stress in as-deposited amorphous silicon and polysilicon films can be as
much as 400 MPa and be either tensile or compressive depending on the deposition
temperature. The transition from tensile to compressive stress is quite sharp and
depends also on other deposition parameters, making it difficult to control the
stress in the as-deposited film. The residual stress in polysilicon deposited at 615°C
can be reduced to –10 MPa (compressive) by annealing for 30 minutes at 1,100°C
in N and that in amorphous silicon films deposited at 580°C is reduced to 10 MPa
2
(tensile) by annealing for 30 minutes at 1,000°C in N . Perhaps more importantly,
2
the residual stress gradient in these films is also reduced to near zero. An alternative
method is to deposit alternating layers of amorphous silicon grown at 570°C and
polysilicon grown at 615°C [4]. The amorphous silicon is tensile and the polysili-
con is compressive. By adjusting the thickness and distribution in a multilayer film,
it is possible to control both the stress and the stress gradient in an as-deposited
polysilicon layer.