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18                                                 Materials and Fabrication Techniques

                 The optical lithography process is illustrated in Figure 2.4. In electron beam lithog-
                 raphy the resist is exposed to an energetic beam of electrons swept across the wafer.
                 The beam is switched off and on to create a pattern in the resist, which again can be
                 either positive or negative. E-beam resist is in general not as thick as optical resist,
                 being of the order of 0.2 to 0.9 µm. Feature sizes are of the order of 10 nm. The mini-
                 mum feature size that can be obtained with conventional lithography is not usually a
                 concern for mechanical MEMS devices. However, other challenges have arisen as
                 the lithography techniques used have expanded beyond the conventional limits.
                 Double-sided and grayscale lithography, thick and laminated photoresists, liftoff
                 processes, and the problems presented by large topographical features are all rele-
                 vant examples.


                 2.3.2.1  Double-Sided Lithography
                 Many MEMS devices require double-sided processing; in the majority of cases this
                 means that the patterns on either side of the wafer have to be aligned to each other.
                 Although some workers have achieved this by etching completely through a wafer
                 to form registration marks on the back side, the difficulties that this presents makes
                 this a less than attractive option. Special alignment equipment is available for
                 double-sided aligning. Some equipment uses an electronically captured image of
                 crosshairs on a mask to which crosshairs on the back side of a wafer can be aligned.
                 The front of the wafer is then exposed through the mask, which is clamped to the
                 equipment. The alignment accuracy that can be achieved is of the order of 1 µm.
                 Other equipment uses an infrared image converter to enable patterns on the
                 backside of a wafer to be viewed on a monitor. The alignment accuracy in
                 this case is limited to about 20 µm for a 4-inch wafer because the pattern on the
                 wafer is separated from that on the mask by the thickness of the silicon wafer.
                 This makes it impossible to focus sharply on both patterns simultaneously. In
                 general, it is advisable to use double-sided polished wafers when using double-
                 sided lithography.


                 2.3.2.2  Grayscale Lithography
                 This is a technique by which topographical features can be formed in photoresist.
                 The amount of resist removed during the development cycle depends on the expo-
                 sure in Joules per square meter, and a graph plotting the amount of resist removed
                 against exposure is called a Gamma curve. The exposure at different pixel points on
                 the resist can be controlled by having different gray levels on the mask. These gray
                 levels are formed by arrays of submicron dots, and the gray level itself can be
                 controlled by the number or size of the dots within the pixel. The important factor
                 is that the dots themselves are not individually resolved by the mask aligner, but
                 serve only to reduce the exposure. The number of gray levels that can be achieved
                 with a times-five wafer stepper that can resolve 0.5-micron features is of the order
                 of 300. In practice, 30 gray levels are sufficient for most applications. In principle,
                 the features formed in the resist can be transferred to the underlying substrate by
                 etching in, for example, an ion beam miller. One application of this technique
                 is the fabrication of microlenses and microlens arrays as shown in the SEM
                 photograph in Figure 2.7.
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