Page 332 - A Practical Guide from Design Planning to Manufacturing

302 Chapter Nine

9. What is meant by a damascene process? What is meant by dual
damascene?
10. [Bonus] Make a list of as many elements as possible that are used
in semiconductor manufacturing and what they are used for.
11. [Bonus] Draw a cross section of the layout in Fig. 9-32 for a cutline
running through the center of the poly line forming the NMOS gate.
12. [Discussion] What are likely to be the most serious manufacturing
obstacles to further process scaling?

Bibliography
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Campbell, Stephen. The Science and Engineering of Microelectronics Fabrication. 2d ed.,
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[Extremely accessible and extremely detailed, this is the best online semiconductor
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Pati, Buno. “Tutorial on Subwavelength Lithography.” Design Automation Conference, New
Orleans, LA: 1999.
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Stix, Gary. “Shrinking Circuits with Water.” Scientific American, July 2005.
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Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1um SRAM Cell.”
IEDM, 2002, pp. 61–64. [A detailed description of Intel’s 90-nm fabrication process.]
U.S. Patent No. 6,329,118. “Method for Patterning Dual Damascene Interconnects Using
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manufacturing flow.]