Page 157 - Microsensors, MEMS and Smart Devices - Gardner Varadhan and Awadelkarim

BURIED OXIDE PROCESS 137

4. Following the silicon etch, a sidewall SiO2 layer of 150 nm is thermally grown
in wet O 2 at 1000°C. The thermal oxidation process reduces possible damage
on the sidewalls of the silicon steps created during the Cl 2/BCl 3/H 2 RIE. The
lateral dimensions of the SCS structures are reduced during the thermal oxidation
(Figure 5.17(d)).
5. A 400 nm layer of Al with a step coverage of 60 percent on the sidewalls is
conformably deposited using DC magnetron sputter deposition in a commercial depo-
sition tool. The sputtering is performed at a pressure of 9 mTorr and at a temperature
of 20 °C in argon gas and a beam current of 5 A. Before the Al deposition, contact
windows are opened to allow electrical contact to both the silicon substrate and the
movable silicon structure (see Figure 5.17(e)).
6. After the Al deposition, positive photoresist is spun on the Al layer at 2.5 krpm
for 45 seconds (3.6 urn thick) to fill the 3.8 urn-deep trenches. An Al side-
electrode pattern is created in the resist using a wafer stepper to expose the resist
(Figure 5.17(f)).
7. The Al side-electrode pattern is then transferred to the Al by means of an aluminum
dry-etch process; this step is required to clear the conformal Al layer deposited on the
high steps where the resist has been removed. The etch process is an anisotropic RIE
process that utilises flow rates of 20 sccm of Cl 2 and 40 sccm of barium trichloride
(BCl 3) at a chamber pressure of 50 mTorr and a DC self-bias voltage of 250 V. The
photolithography and the Al RIE steps produce smooth edges on the Al pattern over
a topography with 3.8 nm steps (Figure 5.17(g)).
8. After the Al electrodes are patterned, the SiO2 is etched back with a CF4 plasma in a
standard parallel-plate RIE tool. Anisotropic etch profiles are preferred to the oxide
etch-back to remove the oxide from the bottom of the trenches but to retain the SiO 2
on the top and sidewalls of the SCS structures. Therefore, a low chamber pressure
of 10 mTorr and a high DC self-bias of 600 V are selected in the CF4 RIE process
(Figure 5.17(h)).

5.5 BURIED OXIDE PROCESS

This process is still under development and is based on the separation by the implanted
oxygen (SIMOX) technique that was developed originally to enable the manufacture of
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silicon-on-insulator (SOI) wafers for ICs . The buried oxide process generates microstruc-
tures by means of exploiting the etching characteristics of a buried layer of SiO 2- After
oxygen has been implanted into a silicon substrate using suitable ion-implantation tech-
niques, high-temperature annealing causes the oxygen ions to interact with the silicon to
form a buried layer of SiO2. The remaining thin layer of SCS can still support the growth
of an epitaxial layer of thickness ranging from a few microns to tens of microns.
In micromachining, the buried SiO2 layer is used as an etch-stop. For example, the
etch rate of an etchant such as KOH slows down markedly as the etchant reaches the
SiO2 layer. However, this process has the potential for generating patterned SiO2 buried
layers by appropriately implanting oxygen.

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An SOI field-effect transistor (FET) microheater for high-temperature gas sensors is described in Chapter 15.