Page 28 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL BUILDING BLOCKS Ronald E. Best 20

Figure 2.10 Plot of averaged phase detector output signal versus phase error θ . In
e
contrast to the EXOR, does not depend on the duty cycle of the signals.

Obviously, the JK-flipflop phase detector is able to maintain phase tracking for phase errors
within the range −π < θ < π. By an analogous consideration, the phase detector gain of the
e
JK- flipflop phase detector is given by

(2.21)

when the logic levels are U or 0, respectively. If, however, these levels are limited by
B
saturation, phase detector gain must be computed from

(2.22)

In contrast to the EXOR gate, the symmetry of the u and u ′ signals is irrelevant, because
2
1
the state of the JK-flipflop is altered only by the positive transitions of these signals.
In the unlocked state, the JK-flipflop phase detector behaves very much the same as the
EXOR and the multiplier phase detectors. When radian frequencies ω and ω ′ are different,
1
2
the output signal u (t) of the JK-flipflop phase detector contains a term whose fundamental
d
radian frequency is ω − ω ′. Higher harmonics are removed by the loop filter. The pull-in
1 2
process of the PLL containing a JK-flipflop phase detector will be discussed in more detail in
Sec. 3.9.3.

Type 4: Phase-frequency detectors (PFDs)

The PFD is the most widely used type of phase detector. As the name implies, its output signal
does not only depend on a phase error but also on a frequency