Page 31 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL BUILDING BLOCKS Ronald E. Best 23
u must be negative; and when it is in the 0 state, u must be zero. Theoretically, u is a
d d d
ternary signal. Most logical circuits used today generate binary signals, but the third state (u d
= 0) can be substituted by a “high-impedance” state.
The circuitry within the dashed box of Fig. 2.11 shows how the u signal is generated.
d
When the UP signal is high, the P-channel MOS transistor conducts, so u equals the positive
d
supply voltage U . When the DN signal is high, the N-channel MOS transistor conducts, so u
B d
is on ground potential. If neither signal is high, both MOS transistors are off, and the output
signal floats—in other words, is in the high-impedance state. Consequently, the output signal
u represents a tristate signal.
d
To see how the PFD works in a real PLL system, we consider the waveforms in Fig. 2.13.
Figure 2.13a shows the (rather theoretical) case where the phase error is zero. It is assumed the
PFD has been in the 0 state initially. The signals u and u ′ are “exactly” in phase here;
1
2
both positive edges of u and u ′ occur “at the same time”; hence, their effects will
1 2
cancel. The PFD then will stay in the 0 state forever.
Figure 2.13b shows the case where u leads. The PFD now toggles between the states 0 and
1
1. If u lags (as shown in Fig. 2.13c), the PFD toggles between states −1 and 0. It is easily
1
seen from the waveforms in Fig. 2.13b and c that u becomes largest when the phase error is
d
positive and approaches 360° (Fig. 2.13b), and smallest when the phase error is negative and
approaches −360° (Fig. 2.13c). If we plot the average signal versus phase error θ , we get
e
a sawtooth function, as shown in Fig. 2.14. Figure 2.14 also shows the average detector output
signal for phase errors greater than 2π or smaller than −2π. When the phase error θ exceeds
e
2π, the PFD behaves as if the phase error recycled at zero; hence, the characteristic curve of
the PFD becomes periodic with period 2π. An analogous consideration can be made for phase
errors smaller than −2π. When the phase error is restricted to the range −2π < θ < 2π, the
e
average signal becomes

(2.23)

In analogy to the JK-flipflop, phase detector gain is computed by

(2.24)

when the logic levels are U or 0, respectively. If, however, these levels are limited by
B
saturation, phase detector gain must be computed from

(2.25)

A comparison of the PFD characteristic (Fig. 2.14) with the characteristic of the JK-flipflop
(Fig. 2.10) does not yet reveal exciting properties. To recognize the bonus offered by the PFD,
we must assume the PLL is unlocked initially. Furthermore, we make the assumption that the