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76 Renewable Energy Devices and Systems with Simulations in MATLAB and ANSYS ®
®

the three reference signals (Ref_U, Ref_V, and Ref_W) and as output either the highest or the lowest
values (see Figure 4.6). By subtracting the highest value from the positive peak amplitude of the car-
rier signal, the length of the first zero vector is obtained. This first zero vector period happens when
all three phases are connected to the positive DC rail. Similarly, this can be done for the lowest value
of the references to obtain the length of the second zero vector, but in this case the negative peak of
the carrier signal is used. This second zero vector is the period when all three phases are connected
to the negative DC rail. Then, by playing with the distribution of these two zero vectors, different
PWM techniques can be obtained. For example, the SVM equally distributes the length of the two
zero vectors during each switching period, while DPWM eliminates one zero vector and uses the
sum of the two, as it can be seen in Figure 4.6. Finally, the signal selector block can be used in order
to choose between the different modulation techniques.

4.4.3 Grid Synchronization

In order to inject electrical energy in a controlled manner into an AC grid, it is essential to synchro-
nize the amplitude, phase, and frequency of the grid voltage. In practice, the electrical grid voltage
is rich in harmonics, due to nonlinear loads, oscillations, etc., which makes the phase, frequency,
and amplitude detection a challenging task. Several algorithms have been proposed in the literature
for synchronization, from which phase-locked loop (PLL) gives the best performance [47]. The PLL
is not a new technology; the analog implementation of a local oscillator, which is synchronized to
a frequency component from a signal, has been successfully used in telecommunications for many
decades. A PLL consists of three main blocks: phase detector (PD), loop filter (LF), and a voltage-
controlled oscillator (VCO) as shown in the block diagram in Figure 4.7. Inside the PD block, the
input signal is multiplied with the VCO output voltage, which mathematically can be expressed as

(
′
( ′
V i = A i sin ω t + ); V = cos ω t + ) ′ θ
θ
 sin( (ωω t ) +−θ θ ′′)  (4.1)
− ′
⋅ ′
ipd
V PD = VV = Ak   ′) ++ )  
i
2  + ( ωωcos ( + t θθ ′ 
where
ω and ω′ are the actual and estimated angular velocity of the grid voltage
θ and θ′ are the actual and estimated phase of the grid voltage
V and V′ are the measured and estimated grid voltages
i
The output signal V consists of a high-frequency component (sum of the two frequencies) and
PD
a low-frequency component (difference of the two frequencies). The duty of LF is to cancel out the
high-frequency component, and in the ideal case, only the first sine term from (4.1) remains. Thus,
the output of the LF block is a quasi-DC component. This has a positive value when the estimated
frequency, given by the VCO block, is above and negative when the estimated frequency is below
the frequency of the measured grid voltage. In this way, the estimated frequency can be controlled
in order to match with the frequency of the measured grid voltage.
A better PLL performance can be achieved by using a quadrature PLL with quadratic signal
generator (QSG), where the quadrature of the tracked frequency component is also created as shown
in Figure 4.7b [48]. The second-order generalized integrator (SOGI) has the advantage compared to
the other QSGs, which works also as a notch filter, rejecting any unwanted frequency components
[49]. However, when the grid frequency varies, the SOGI has also to adapt to it, which can be done
by using a frequency-locked loop (FLL), which is presented at the bottom of Figure 4.7b [50].
For three-phase systems, the quadrature signal can be obtained by applying the Clarke transforma-
tion; thus, the quadrature PLL can be adopted directly. This method is called synchronous reference