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SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING 3.7

The fundamental reasons for the use of epitaxial wafers are several fold.
• A common failure mode of CMOS devices is a phenomenon called latch-up. This is a case where
vertical pnp and lateral npn bipolar structures can switch on and draw excess current resulting in the
destruction of the device. This is effectively prevented by having a high-conductivity (heavily doped)
substrate under the lightly doped epitaxial layer in which the circuits reside. Heavy doping prevents
the generation of stray charge carriers in the substrates. A further advantage of heavily doped sub-
strates is conferring immunity from soft errors to the circuits. Soft errors are a result of stray a par-
ticles either from radioactive packaging materials or cosmic rays generating unwanted charge carriers
(electron-hole pairs) that upset the state (on or off) of a transistor in the semiconductor.
• A second reason for epitaxy is to achieve high bulk and surface quality silicon for device fabrica-
tion. Since modern day integrated circuits are, essentially devices very close to the surface of the
wafer—within about a micron of the surface—the surface quality, in terms of impurities and
defects, is critical for the high-yield manufacture of high-performance products. Vapor deposited
epitaxial silicon on single crystal silicon wafers can display higher quality than melt grown crys-
tals. Surface quality, the uniformity of dopants through the film, and control over the resistivity of
the silicon are superior in epitaxial films.
• A third reason for the attraction of epitaxial wafers is the opportunity to achieve vastly different
resistivities between the substrate and the epitaxial layer. For example, typical epitaxial wafers
have substrate resistivities as low as 0.005 Ω-cm while the overlying epitaxial film can have a
resistivity approximately equal to 1 Ω-cm. The heavily doped substrate, which is doped with
boron, performs several functions. Heavy doping in the substrate suppresses latch-up failure, as
discussed earlier. The high concentration of boron can function as a gettering medium for metals,
with particular reference to iron. A phenomenon known as solubility-enhanced gettering results
in the attraction and trapping of iron by the heavily doped substrate, thus removing the metals from
the top, lightly doped epitaxial layer in which the active devices reside. The gettering efficiency
of the substrate is also enhanced by precipitated oxide particles that are formed as a combined con-
sequence of the presence of a high concentration of oxygen in the substrate wafer and the heat
treatments associated with epitaxial deposition and subsequent wafer processing. Since the top epi-
taxial layer is formed by vapor deposition it will be free of oxygen and consequently no precipitates
form in this region. Heavily doped substrates also assist in suppressing the electrostatic discharge
(ESD) failure of integrated circuits. ESD is a phenomenon whereby stray electric charges destroy
devices and circuits. A heavily doped substrate effectively conducts away stray charges preventing
ESD failure. Figure 3.5 shows schematically a cross section of a CMOS transistor in an epitaxial
wafer with the various attributes of epitaxial wafers.

3.4.3 Silicon-on-Insulator Wafers

The original concept of integrated circuits, as conceived by Noyce and Kilby, involved building mul-
tiple transistors in the same piece of silicon, electrically isolated from each other using reverse-biased
p-n junctions, a process called junction isolation. With increasing shrinks and higher functionality of cir-
cuits, junction isolation was found to be inadequate for a number of reasons including the increased
capacitance introduced by the junctions, which in turn adversely impacts the switching speed, the
propensity for excessive junction leakage, and the increased space occupied by the isolating junc-
tions. Consequently a transition has occurred to dielectric isolation with advanced products relying
on shallow trench isolation where shallow, etched trenches filled with silicon dioxide surround the
transistors. A further extension of this process is to provide a dielectric underneath the transistors as
well as to, essentially, completely surround the transistor with an oxide on all sides. The use of a
dielectric layer, underneath the transistors, resulted in the development of silicon-on-insulator (SOI)
wafers wherein a thin, active device layer is separated from the bulk of the wafer by a thin, buried
oxide. The thickness of the top layer, in which the devices are built, varies depending on device
designs with the trend being in the direction of ever-thinner films on the top. 4,5

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