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Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 4

COPPER, LOW-k DIELECTRICS,
AND THEIR RELIABILITY

Hazara S. Rathore
Kaushik Chanda
IBM
Hopewell Junction, New York

4.1 INTRODUCTION

Interconnects or wiring systems distribute clock and other signals and provide power/ground to var-
ious systems on a chip. One of the figures of merit for a high-performing interconnect system is its
RC time delay. As geometries shrink in accordance with Moore’s law, this factor has become a bot-
tleneck in achieving high-speed transmission for advanced microprocessors. Figure 4.1 shows the
increasing dominance of wiring delay versus gate delay with scaling. The 1994 National Technology
Roadmap for Semiconductors (NTRS) described the first needs for new conductor and dielectric
materials that would be necessary to meet the projected overall technology requirements. A lower
resistivity material in conjunction with a lower dielectric constant insulator was required to reduce
the capacitive load of interconnects.
Copper replaced aluminum as an interconnect material of choice due to its lower resistivity and
1
capacitance reduction by scaling of 1x level heights. Copper integration required several modifica-
tions to the existing aluminum technology. New process steps like “damascene,” electrochemical
deposition, and chemical mechanical polishing (CMP) were introduced. In addition, process ele-
ments like liners, hardmasks, seed layers, and caps were necessary for the integration scheme.
Reliability concerns with copper and its interaction with the surrounding dielectric became an inte-
gral part of most technology qualifications. Section 4.2 briefly describes the copper interconnect
technology. It discusses the advantages and limitations, along with the integration complexities.
Several materials, both organic and inorganic based, are being evaluated to replace the traditional
back end-of-line (BEOL) SiO as dielectric. This choice of the dielectric material depends on several
2
factors. Electrical properties such as dielectric constant, intrinsic leakage, breakdown field, and
physical properties like stability, moisture absorption, bulk modulus, and coefficient of thermal
expansion are critical to making the choice. The material’s integration with copper and their relia-
bility are vital to the success of such an advanced interconnect scheme. For example, mismatch in
the mechanical properties of copper and low-k dielectrics can lead to reliability concerns like stress
voiding, thermal fatigue, and chip package interactions. Poor thermal conductivity of the surround-
ing dielectric has become a factor in determining the allowable current densities through copper
lines. Also, with the introduction of hardmasks and caps (higher dielectric constant materials), the
effective dielectric constant of the whole stack instead of the bulk dielectric constant of the material

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