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                                       SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING

                                                          SILICON SUBSTRATES FOR SEMICONDUCTOR MANUFACTURING  3.13

                                  different resistivity, or conductivity type from the substrate was the first case of integrating two layers
                                  with differing properties. Extensions of this concept have been SOI wafers and strained silicon lay-
                                  ers using Si-Ge heteroepitaxy, which involve integrating different materials (e.g., oxides, alloys such
                                  as Si-Ge) with silicon. The significant advances in wafer bonding technology have enabled the inte-
                                  gration of materials that are not lattice matched with silicon, may exhibit different coefficients of
                                  thermal expansion and have no chemical or physical similarities or affinity with silicon. However,
                                  for good wafer bonding a few key requirements have to be borne in mind:
                                  • The material to be bonded to silicon has to be stable at the bonding temperatures and in subsequent
                                   wafer processing operations.
                                  • For good bond quality, excellent surface quality, flatness, planarity, and cleanliness of the two
                                   materials being bonded are essential.
                                  • Frequently the presence of a silicon oxide film between the silicon substrate and the material to be
                                   bonded aids in achieving good bonding.
                                  • Clearly, bonding is most viable when the two wafers being bonded are of the same diameter.
                                   However, with certain materials such as optoelectronic materials this is not currently possible.
                                   Materials such as gallium asenide, indium phosphide, indium antimonide cannot be produced as
                                   large area wafers since crystal growth technology for these materials is much less well developed
                                   as compared to silicon. Consequent attempts at bonding smaller wafers to larger silicon wafers to
                                   enable the processing of the composite wafer in conventional silicon wafer fabrication facilities are
                                   tentatively being explored.
                                    One material of interest, in the context of increased carrier mobility, is germanium. Compared with
                                  silicon, germanium has a smaller carrier transport mass and a smaller energy gap. Both these lead to
                                  a higher drive current I  but also a higher off-stage leakage current I . As a consequence of the
                                                   on                                 off
                                  increased off-stage leakage current, combining germanium with silicon would have to be in an SOI,
                                  or GeOI, configuration with an oxide between the top germanium layer and the silicon substrate. 9,16
                                  Thermal Issues. An increasing problem with higher density of transistors in advanced logic prod-
                                  ucts is the higher power consumed by such circuits and the higher operating temperatures of such cir-
                                  cuits. In particular, high-performance microprocessors have to deal with local hot spots, often called
                                  fire ball zones at the core of the circuits. The high local temperatures associated with these regions
                                  limit the performance of the products. Consequently means for spreading the heat from the local hot
                                  spots, such that the peak temperature approaches the average temperature of the die, are required.
                                    A technology that has been proposed to achieve this embeds diamond films, synthesized by CVD
                                  techniques, into silicon wafers to fabricate, the wafers called  silicon-on-diamond (SOD) wafers.
                                  Diamond has the highest thermal conductivity of all known materials and placing a diamond film in
                                  close proximity to the transistors in a silicon film on the diamond layer is the most effective way of
                                  spreading heat from hot spots and thus enabling higher performance and better reliability. One
                                  scheme for fabrication of SOD wafers is described in Ref. 17. Combining diamond with silicon
                                  would represent another case of enhancing silicon with other materials.


                      3.5 KEY ISSUES AND CHALLENGES IN THE MANUFACTURE
                      OF SILICON SUBSTRATES

                                  The primary issues and challenges in manufacturing silicon substrates can broadly be divided into
                                  the following:
                                  1. In order to keep up with the needs of the technologies for the scaling of silicon, there is a con-
                                    tinuing drive to improve wafer quality, with particular references to defects and improved wafer
                                    flatness. These are topics of intense interest to the user community, the manufacturers of semi-
                                    conductor products.


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