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8.4 Ideal DSP Architectures 367

8.4.2 Storage Elements

The storage elements (SE) or memory elements (M) shall store data so that the pro-
cessing element, in addition to implementing the algorithm, can access appropri-
ate data without loss of any computational time slots. Since the processing
elements normally require several simultaneous inputs and outputs, we assume
that the memories are partitioned into several independent memories, or have
several ports, which can be accessed in parallel. The important issues are the
access mechanism for the memories, the bandwidth, and the number of ports. Fur-
thermore, the storage shall be efficient, since memories are expensive in terms of
chip area. The memories must also have reasonable form factors—i.e., the ratio of
the number of words (height) and the word length (width).

8.4.3 Interconnection Networks
The interconnection network (/CAT) shall provide the communication channels
needed to supply the PEs with proper data and parameters, and store the results
in the proper memories. The data movement should be kept simple, regular and
uniform. Major design issues involve the topology of the communication network
and its bandwidth.

8.4.4 Control
It is harder to command than to obey.
F. Nietzsche

There are two types of control signals: one type for setting up control and commu-
nication paths and another type for loading information into the memories [2]. The
first type needs to be valid only in time intervals during which the second type has
significant transitions. The second type is used to capture values and store them
into the memories. Since they define the basic units of time, they are called clocks.
An important issue is the control strategy used to coordinate activities
between the architectural components. Control strategy is mainly concerned with
the manner in which control signals direct the data flow in the system. In a cen-
tralized control scheme, all the control signals come from a single source. Obvi-
ously, the central controller is a critical part in a system and may become a
bottleneck that affects the performance and reliability of the entire system. The
central controller must therefore be carefully designed to achieve good system per-
formance. These drawbacks can be somewhat alleviated by using a distributed
control strategy in which a small controller is associated with each operational
unit in the system. In multiprocessor systems, which are further discussed in sec-
tions 8.5 through 8.9, control of crossbar interconnection networks is usually
decentralized while multiple-bus interconnection networks can use either central-
ized or decentralized control.
At present, there is no general architecture suitable for the design of all types
of control units. In [2], different implementation techniques commonly used in
microprocessors are discussed. However, the simple and static computational
structure that characterizes most DSP algorithms allows the use of far less com-
plex control schemes than the one used in general-purpose computers.