Page 431 - DSP Integrated Circuits

416 Chapter 9 Synthesis of DSP Architectures

An advantage is that the high-speed, bit-serial interconnection network is
fixed and does not require any control signals. However, a switching function is
required on the bit-parallel side. We must decide which of the two serial/parallel
GS/P) converters the RAM should be using. Further, address generation for the
RAM can be designed so that this control becomes simple.

Architecture 4
The fourth architecture is obtained by using the second alternative for PEs and
the first alternative for the RAMs. This architecture is characterized by the follow-
ing constraint:
The variables with indices 0 to N/2 — 1 are assigned to RAMo and the rest
toRAMi.
A RAM is not connected to both inputs of a butterfly PE.

It is not possible to find an architecture with these properties since they are
contradictory. This can be explained from Figure 7.71. For example, in the second
stage a butterfly uses data with indices i = 0 and i+N/4: = 4. According to the first
constraint just listed, these data are assigned to the same RAM, but according to
the second constraint, this is not allowed.
The main advantage of having no, or few, switches is that control becomes
simpler. In order to evaluate the three feasible architectures properly, we must
investigate the complexity of control of the architectures. We have elected to evalu-
ate the third architecture since it lacks switches and since the shift registers have
fixed connections to the butterfly PE.

9.9.2 Re-Partitioning the FFT

In the previous sections we have performed resource allocation and assignment for
the processes that perform the arithmetic operations involved in the FFT. Also, we
have chosen to continue the design on the third architecture alternative. This
means we have decided which butterfly PE will perform a certain butterfly pro-
cess, and which memory cell will store a particular data item. We must now design
the control processes that control the architecture according to this assignment.
Data must be read from the memories, communication channels must be set up,
coefficients must be sent to the butterfly PEs, etc. The control processes consists of
the address generators for RAM, ROM, cache memories, and the two loops. In this
section we will repartition the design to find suitable processes to control the
architecture. It will also be shown that it is possible to map the resulting processes
directly onto hardware structures.

Address Generation for the FFT
In the section about RAM allocation and assignment we described two different
assignment schemes. In the first scheme, the first half of the FFT variables were
assigned to the first RAM and the second half to the second. In the second, the
variables were assigned to RAM using an XOR pattern. The assignment of specific
data can be found by evaluating the P function in the first assignment alternative.
However, we need not necessarily evaluate this function in the address generation.
The address in a RAM is not necessarily equal to the index of a variable.
In this section we will find a mapping from data index to RAM address. Address
generation for the RAMs could then be split into several processes, one for each mem-