Page 439 - DSP Integrated Circuits

424 Chapter 9 Synthesis of DSP Architectures

end if;
if Do_in = FFTStage then
ifN s_in = (N/2)then
BF := N s_in/2;
else
BF := 2 * Ns_in;
end if;
ifP_in = Othen
Aoo_out = ki_in mod(N/2);
Ai 0_out = (k!_in + Ng_in + BF) mod(N/2);
else
A 0o_out = (ki_in + BF) mod(N/2);
Aio_out = (ki_in + Ns_in) mod(N/2);
end if;
end if;
if Do_in = Output then
ifP_in = Othen
A_out := is_in;
end if;
end if;
end Address_Gen_0;

Box 9.5 Behavior of address generator 0

architecture Beh_Address_Gen_l of Address_Gen_l is

begin
if Do_in = Input then
if P_in = 1 then
A_out := i_in;
end if;
end if;
if Do_in = FFTStage then
ifNs_in = (N/2)then
BF := N s_in/2
else
BF := 2 * Ns_m;
end if;
ifP_in = Othen
Aoi_out = (ki_in + Ns_in) mod(N/2);
A n_out = (ki_in + BF) mod(N/2);
else
A 0i_out = (k!_in + N s_in + BF) mod(N/2);
An_out = ki_in mod(N/2);
end if;
end if;
if Do_in = Output then
ifP_in = Othen
A_out := is_in;
end if;
end if;
end Address_Gen_l;

Box 9.6 Behavior of address generator 1