Page 437 - DSP Integrated Circuits

422 Chapter 9 Synthesis of DSP Architectures

Figure 9.37 The final architecture

a binary counter. In the input and output phases, the base index is used almost
directly as an address to a RAM.
The base index generator must evaluate which RAM a data word belongs to
and send this RAM the base index. In the output phase, the index must be digit
reversed before being used as an address. Also, during the input and output
phases the I/O interface must be controlled. In the FFT computation phase the
base index is first Gray encoded and then sent to the address generators, which
extend it with the appropriate bits.
Next summarize the behavioral descriptions of the address generation pro-
cesses. The behavior of the stage process is described in Box 9.3 while the behavior
of base index generator is described in Box 9.4. The behaviors of Address Genera-
tor 0 and Address Generator 1 are described in Boxes 9.5 and 9.6, respectively.