Page 442 - DSP Integrated Circuits

9.11 SIC (Single-Instruction Computer) 427

returned to the output cell of the PE. The SIC can therefore be viewed as an inter-
communication processor.
The PEs are asynchronous and work only when they have valid input data.
Power is thereby conserved. We assume that most of the PEs perform large compu-
tational tasks, so they are slow compared with shared memory. In practice, bit-
serial PEs are efficient in terms of power consumption, chip area, and throughput.
New functions can easily be added by providing new PEs. No new op-codes are
required. This simplifies the designer's trade-off between hardware and software.
The system can be updated as new and improved PEs become available, thereby
prolonging its lifetime.
This approach places emphasis on communication issues in the real-time sys-
tem. We will later describe how conventional programming constructs can be
implemented, if needed, in the processor.

9.11.1 Partitioning of Large DSP Systems
A large DSP system can usu-
ally be partitioned into a set
of subsystems. Each of these
subsystems can be imple-
mented by an SIC processor
having its own shared-mem-
ory address space, as illus-
trated in Figure 9.41.
Typically each SIC has only Figure 9.41 Large DSP system that is implemented
a few PEs to achieve balance as co-operating SIC processors
between communication
bandwidth and computa-
tional capacity. It is possible to connect SIC processors that implement the sub-
systems according to the organization of the large DSP system. Hence, several of
these SIC processors can be used in parallel, cascade, or hierarchical fashion as
illustrated in Figure 9.41. Compare also with Figures 9.26 through 9.28.
It is possible to use a mix of different types of processors within the same
memory address space. A standard DSP may, for example, be substituted for one of
the PEs in the SIC processor. This nonhomogeneous multiprocessor architecture
allows the same framework to be used for a wide range of applications.
Notice that the use of high-level DSP operations will significantly reduce the
complexity of programming the highly pipelined, nonhomogeneous multiprocessor
system. This would otherwise become a major problem.

9.11.2 Implementation of Various SIC Items

Programming concepts such as subroutines, interrupts, and local variables, can be
easily implemented as illustrated in Figure 9.42.

The Single Instruction Since there is only one move instruction, no instruc-
tion decoding is necessary. The program memory (PM) need only contain the
source address and the destination address of the moves.