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430 Chapter 9 Synthesis of DSP Architectures
[15] Goor van de A.J.: Computer Architecture and Design, Addison-Wesley,
Wookingham, England, 1989.
[16] Hartley R. and Jasica J.: Behavioral to Structural Translation in a Bit-Serial
Silicon Compiler, IEEE Trans, on Computer-Aided Design, Vol. CAD-7, No. 8,
pp. 877-886, Aug. 1988.
[17] Jain R., Catthoor R, Vanhoof J., De Loore B.J.S., Goossens G., Goncalvez
N.F., Claesen L.J.M., Ginderdeuren van J.K.J., Vandewalle J., and De Man
H.J.: Custom Design of a VLSI PCM-FDM Transmultiplexor from System
Specifications to Circuit Layout Using a Computer-Aided Design System,
IEEE Circuits and Systems, Vol. CAS-33, No. 2, pp. 183-195, Feb. 1986.
[18] Rung S.Y.: VLSI Array Processors, Prentice Hall, Englewood Cliffs, New
Jersey, 1988.
[19] Lipovski G.J.: Architecture of a Simple, Effective Control Processor, Second
Symposium on Micro Architecture, EUROMICRO, pp. 187-194,1976.
[20] McCanny J., McWhirter J., and Swartzlander Jr. E.E. (eds.): Systolic Array
Processors, Prentice Hall, London, 1989.
[21] Murray A.F. and Denyer P.B.: A CMOS Design Strategy for Bit-Serial Signal
Processing, IEEE J. on Solid-State Circuits, Vol. SC-20, No. 3, pp. 746-753,
June 1985.
[22] Nordhamn E., Sikstrom B., and Wanhammar L.: Design of an FFT Processor,
Fourth Swedish Workshop on Computer Architecture, DSA-92, Linkoping,
Sweden, Jan. 1992.
[23] Nordhamn E.: Design of an Application-Specific FFT Processor, Linkoping
Studies in Science and Technology, Thesis, No. 324, Linkoping University,
Sweden, June 1992.
[24] Note S., Meerbergen van J., Catthoor F., and De Man H.J.: Automated
Synthesis of a High Speed Cordic Algorithm with CATHEDRAL III
Compilation System, IEEE Inter, symmp. on circuts and systems, ISCAS-88,
Espoo, Finland, June 6-9,1988.
[25] Rabaey J., De Man H.J., Vanhoof J., Goossens G., and Catthoor F:
CATHEDRAL II: A Synthesis System for Multi-Processor DSP Systems, in
Gajski (ed.), Silicon Compilation, pp. 311-360,1988.
[26] Sikstrom B., Wanhammar L., Afghahi M., and Pencz J.: A High Speed 2-D
Discrete Cosine Transform Chip, Proc. 2nd Nordic Symp. on VLSI in
Computers and Communications, Linkoping, Sweden, June 2-4,1986.
[27] Sikstrom B., Wanhammar L., Afghahi M., and Pencz J.: A High Speed 2-D
Discrete Cosine Transform Chip, Integration, the VLSI Journal, Vol. 5, No. 2,
pp. 159-169, June 1987.
[28] Smith S.G., Denyer P.B., Renshaw D., Asada K., Coplan K.P., Keightley M.,
and Mhar J.I.: Full-Span Structural Compilation of DSP Hardware, Proc.
ICASSP-87, pp. 495-499,1987.
[29] Swartzlander Jr. E.E.: VLSI Signal Processing Systems, Kluwer Academic
Pub., Boston, 1986.
[30] Torkelson M.: Design of Applications Specific Digital Signal Processors, Diss.
158, Lund University, Sweden, 1990.
[31] Wanhammar L.: Implementation of Wave Digital Filters with Distributed
Arithmetic, Proc. 4th Intern. Symp. on Network Theory, Ljubljana,
Yugoslavia, pp. 385-397, Sept. 1979.

