Page 450 - DSP Integrated Circuits

Problems 435

(c) Determine the required clock frequency for the PEs.
(d) Determine the required number of memories when the memory word
length is the same as the data word length.
(e) Estimate the size of the RAMs.
(f) Select the number of RAMs when the form factor < 1:4.
(g) Determine the communication network.
9.16 Determine the number of shimming delays required in the 2-D DCT
processor shown in Figure 9.38.
9.17 Show how transposition is accomplished in the 2-D DCT processor. See
Figure 9.39.
9.18 Verify the four architectural alternatives discussed in section 9.9.
9.19 Complete the behavioral descriptions in Boxes 9.4 through 9.6.
9.20 Estimate the reduction in power consumption for the implementation
discussed in Example 7.3 if the power supply voltage is reduced to a
minimum. The required sample rate is only 10 MHz. Assume that I Vfn I ~
I V Tp I - 0.7 volt.
9.21 Develop an SIC architecture suitable for the adaptive FIR filters discussed in
section 3.14.1.