Page 449 - DSP Integrated Circuits

434 Chapter 9 Synthesis of DSP Architectures

Q Processing time of 14 clock cycles
Q Maximum clock frequency for CMOS, fai = 120 MHz
Q Read-write time for the RAMs, T read = T wri te = 17 ns

(a) Determine the number of PEs and a suitable PE schedule.
(b) Suggest an architecture. Specify the PEs, memories, I/O, communication
channels, and control.
(c) Determine the required clock frequency for the PEs.
(d) Determine the required number of memories when the memory word
length is the same as the data word length.
(e) Determine the size of the RAMs.
(f) Select the number of RAMs when the form factor < 1:4.
(g) Determine the communication network.
9.14 An FFT processor meeting the following specification shall be implemented:
Q 1024 complex points
Q Processing time < 1 ms
Q Data word length of W d = 21 bits
Q The PEs implementing a butterfly
Q Processing time of 23 clock cycles
Q Maximum clock frequency for CMOS, fci = 120 MHz
Q Read-write time for the RAMs, T reac[ = T wri te = 17 ns

(a) Determine the number of PEs and a suitable PE schedule.
(b) Suggest a suitable architecture. Specify the PEs, memories, I/O,
communication channels, and control.
(c) Determine the required clock frequency for the PEs.
(d) Determine the required number of memories when the memory word
length is the same as the data word length.
(e) Determine the size of the RAMs.
(f) Select the number of RAMs when the form factor < 1:4.
(g) Determine the communication network.
9.15 An interpolating wave digital filter meeting the following specification shall
be implemented:

Interpolation with a factor 16 in 4 stages
Two signal channels
Sampling frequency (input) = 44.1 kHz
Sampling frequency (output) = 16 • 44.1 = 705.6 kHz
Filter orders of 17, 9, 5, and 5
The adaptors in each stage of operating at the lower sample rate
Data word length of Wj = 22 bits
Coefficient word length of W c = 14 bits
PE implementing a two-port adaptor
Processing time of 24 clock cycles
Maximum clock frequency for CMOS, /CL = 120 MHz
Read-write time for the RAMs, T rea^ = T wri te = 17 ns
(a) Determine the number of PEs and a suitable PE schedule.
(b) Suggest an architecture. Specify the PEs, memories, I/O, communication
channels, and control.