Page 466 - DSP Integrated Circuits

10.6 Asynchronous Systems 451

In an asynchronous system the subsystems are not required to wait on each
other, and the transfer of information between combinational blocks is not per-
formed in synchrony with a global clock signal, but rather at times is determined
by the latencies of the blocks themselves. In the asynchronous scheme, processing
time approaches an average for all tasks rather than being set by a clock period in
the worst-case completion time of all tasks.
A self-timed circuit is a circuit that performs computational steps whose initi-
ation is caused by signal evens at its inputs and whose completion is indicated by
signal events at its outputs. Self-timed systems, (a subclass of asynchronous sys-
tems) are legal interconnections of self-timed circuits.
A circuit is delay-insensitive when its correct operation is independent of any
assumptions on delays of operators and wires except that delays are finite [22].
Such circuits do not use a clock signal or knowledge about delays. It has been
proved in [16] that the class of delay-insensitive circuits is very limited. Different
asynchronous techniques distinguish themselves in the choice of the compromises
to delay-insensitivity.
A speed-independent system, with zero-delay wires, implements a logic behav-
ior independent of delay in the logic modules, but there are no delays in wires.
Self-timed techniques assume that a circuit can be decomposed into equipotential
regions inside which wire delays are negligible [24].
Communication between two asynchronous systems is subject to a communi-
cation protocol, as illustrated in Figure 10.24. Four-phase signaling is one such
protocol that will be discussed later.
Self-timed circuits are a means of synchronizing different blocks at a local
level, thereby alleviating problems associated with distributing global clock sig-
nals over the entire face of the chip. Most designers agree that asynchronous
transfer of information is required at the higher levels in a complex system, but
may disagree on how small the appropriate block size should be. However, it
seems unreasonable to use blocks consisting of a single gate, due to the overhead
associated with asynchronous transfers. As the speed of the technology has
increased, block size has shrunk. Self-timed circuits, in addition to performing
some logic function, provide a completion signal to indicate when the computation
is finished.

Figure 10.24 Communication between two asynchronous systems