Page 567 - DSP Integrated Circuits

552 Chapter 12 Integrated Circuit Design

The two major factors that influence the yield of an 1C process line are the
maturity of the line and the size of the dice. New process lines tend to have low
yields in their infancy, but the yields tend to improve with processing experience
and fine-tuning of the processing steps. A measure of performance for a process
2
line is the number of defects/cm . It is assumed that any defects falling within the
active area of a given chip will cause that chip to fail. Typical defect densities are
2
in the range D ~ 0.5 to 5 defects/cm . Hence, the yield will be low for large chips.
The simplest model of the yield is (Poisson distribution)

where d = device density (percent active area), A = die area, and D = defect density.
The Poisson model assumes that defects are uniformly distributed across the area of
the wafer. In practice, however, actual yield results show a somewhat slower descent
of yield with increasing chip area than predicted by the Poisson model. A more accu-
rate model for large dice (d AD > 1) is the composite Murphy-Moore's model:

In practice the yield is somewhat lower for dice close to the wafer periphery—
i.e., the outermost 10 mm. Further, a number of circuits may be damaged during
testing, bonding, etc.

EXAMPLE 12.2
Estimate the number of working chips from a batch of 50 wafers of diameter 6
2
inches ~ 150 mm when the dice are square with an area of 120 mm . The defect
2
density is 2 defects/cm . Assume that the device density—i.e., the area susceptible
to defects, is d = 0.7.
We have d A D = 0.7 • 120 • 0.02 = 1.68

The estimated number of working chips is

REFERENCES

[1] Bakoglu H.B.: Circuits, Interconnections, and Packaging for VLSI, Addison-
Wesley, Reading, MA, 1990.
[2] Cai H. and Hegge J.J.A.: Comparison of Floorplanning Algorithms for Full
Custom ICs, IEEE 1988 Custom Integrated Circuit Conf., pp. 7.2.1-7.2.4,
Rochester, NY, May 1988.