Page 569 - DSP Integrated Circuits

554 Chapter 12 Integrated Circuit Design

PROBLEMS

12.1 Estimate the unit cost, excluding development costs, for the FFT processor in
the case study when
(a) 500 (b)5000 (c) 500,000
units are to be produced. Make the appropriate assumptions.
12.2 What is a slicing floor plan? What are its advantages and disadvantages?
12.3 Estimate the power consumption for the FFT processor if the two RAMs are
placed off-chip.
12.4 The required clock frequency of a commercial CMOS circuit is 50 MHz. The
chip is estimated to dissipate 0.4 W and is housed in a plastic chip carrier
that has an effective thermal resistance of 172 °C/W. The process spread is
±35% and the variation in power supply is ±5%. Estimate the required
design margin for the clock frequency.
12.5 Is it possible to significantly reduce the power consumption for the FFT
processor by using another logic style for the shift-accumulators?
12.6 Estimate the power consumption for the FFT processor if the execution time
is increased to 2 us.

12.7 Estimate the required chip area and power consumption if an FIR filter
solution is used for the interpolator.
12.8 Estimate the potential reduction in power consumption that is possible by
using only power supply voltage scaling for the case studies involving a
(a) DCT processor
(b) Interpolator
Assume that the maximal clock frequency is

where a » 1.55, V T = 0.7 V, and a 12-bit S/P multiplier in the logic style [8, 9]
2
typically requires 0.25 mm and 35 mW at 250 MHz and 3 V.
12.9 Estimate the potential reduction in power consumption that is possible by
using both power supply voltage scaling and a modified architecture for the
case studies involving a
(a) DCT processor
(b) Interpolator