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7.7 INTRODUCTION TO FPGAS AND OTHER GENERAL-PURPOSE DEVICES 317

7.7 INTRODUCTION TO FPGAs AND OTHER GENERAL-PURPOSE DEVICES

The devices briefly discussed in this section vary in size from SSI to LSI circuit modules and
range greatly in complexity from simple gate-level modules to those having a multiplicity of
components, including flip-flops. Of the general purpose devices, the simplest are the AND-
OR-invert or OR-AND-invert type devices with logic equivalent gate counts numbering
typically in the three to five range. These SSI circuits are often used as building blocks in
complex logic devices. Then, within the PLD spectrum of devices, the most complex class
belongs to the field programmable gate array (FPGA) devices, which may contain a variety
of primitive components, including discrete gates, MUXs, and flip-flops. Since this chapter
deals only with combinational logic devices, the treatment here will deal mostly with those
PLDs and general-purpose devices that are combinational in character.
The discussions to this point in the text have dealt only with combinational logic, con-
sequently, the reader is not expected to grasp the significance of flip-flop operation in the
output logic stage to some PLDs. The use of these "registered" PLDs will become evident in
later chapters when sequential machines are discussed in detail. Treatment here will begin
with simple general-purpose building block devices and will end with an introduction to
the complex FPGAs.

7.7.1 AND-OR-lnvert and OR-AND-lnvert Building Blocks
Just as the XOR and EQV functions can be implemented by what amounts to one gate
level of MOS transistors as in Figs. 3.26 and 3.27, so also can the AND-OR-invert and
OR-AND-invert functions be implemented with just one gate level of transistors. Shown
in Fig. 7.21a is the CMOS realization of the AND-OR-invert (AOI) gate. It is called a
gate since it is a CMOS SSI circuit and has a propagation delay equivalent to that of a
single NAND or NOR gate. There are many useful applications of this basic building block,
including integration with much larger PLD logic blocks. The physical truth table and its
mixed-logic interpretation are presented in Figs. 7.21b and 7.21c, respectively. The output
logic expression can be read directly from the mixed-logic truth table and is

F(L) = [AB + CD](L), (7.3)
which results in the logic equivalent circuit for the AOI gate shown in Fig. 7.2Id.
As a simple example of the use of the AOI gate, consider the two-level active low EQV
function given by
F(L) = (AB+AB)(L).

This function can be implemented in Fig. 7.2Id by connecting A to C and B to D via two
inverters, a transistor count of 12. In comparison, the EQV gate of Fig. 3.27a requires only
six transistors.
The CMOS realization of the OR-AND-invert (OAI) gate is the dual of that for the AND-
OR-invert gate and is easily obtained by flipping the latter end-for-end while interchanging
all NMOS with PMOS and vice versa. This is done in Fig. 7.22a. The same duality exists
between the truth tables of Figs. 7.21 and 7.22, where H's and Us are interchange between
physical truth tables and 1's and O's are interchanged between mixed-logic truth tables. The
output expression for the OAI gate is obtained directly from Fig. 7.22c by reading the O's