Page 400 - Engineering Digital Design

8.9 DUAL-RAIL SYSTEMS AND ALUs WITH COMPLETION SIGNALS 371

are inputs specific to the 7th module and those that are global (applied to all modules in a
cascaded system). Specific to the 7th PALU module are the operands inputs Aj, Bj, Bj^\,
and Bj-\. The Bj_i input arrives from the B input to the next LSB stage in a cascaded
configuration and is necessary for left shifting. Similarly, the Bj +\ input arrives from the B
input to the next MSB stage to permit right shifting. The input and output dual-rail carries
shown in Fig. 8.40 are also specific to the 7th module and are defined as follows:

C,,,0 = carry-in 0 to stage 7 from stage J — I
Ci n 1 = carry-in 1 to stage J from stage 7 — 1
(8.20)
C ou!Q = carry-out 0 to stage 7 + 1 from stage J
C out 1 = carry-out 1 to stage 7 + 1 from stage 7

The meaning here is that C/ nO = 1 when the carry-in to the 7th stage is logic 0, and C\ n 1 = 1
when the carry-in to the 7th is logic 1. Thus, both carry-in parameters cannot be active at
the same time. Similarly, C outO = 1 when carry-out to the (J + l)th is logic 0, or C OM\ = I
when the carry to the (7 + l)th is logic 1, where again only one carry parameter can be
active at any given time.
The global inputs to the PALU include the two mode control inputs, MI and MO, the
function generate signals, F 3, F 2, F\, and FQ, a shift-direction input L/R (meaning right,
"not left" when active), an add/subtract input Add/Sub (meaning subtract, not add when
active), and a start signal called GO. The add/subtract control input operates the same as
that use for the adder/subtractor design in Subsection 8.3.1, but only if the mode control
MQ = 0 according to Fig. 8.39. Also, the shift-direction control L/R is operational only if
mode control M\ = 1, as indicated in Fig. 8.39.
The two outputs, Donej and Rj, are specific to the 7th PALU mudule. When the 7th
stage result of a bitwise logic operation or arithmetic operation is indicated by the output
Rj, a completion signal Donej is issued. However, it is the requirement of an n-bit PALU
design that a final (overall) completion signal, DONE, will not be issued until the Done
signals from all n stages have become active. Thus, the results from those n stages must not
be read until the final DONE has emerged.

Logic Module The logic module is responsible for carrying out both the 16 bitwise logic
operations given by Eq. (8.19) and the shift left or right operation with 0 or 1 fill. (See Section
6.8 for details of a combinational shifter.) Presented in Fig. 8.41 are the output parameters,
Xj,T\, and TO, for the 7th PALU logic module. The output function Xj , representing the
mode control settings for logic and shift operations (according to Fig. 8.39), is given by the
truth table and EV K-map in Figs. 8.4la and 8.41b. The dual-rail outputs from the logic
module, T\ and TO, are defined in the truth table of Fig. 8.41c and represent only logic and
shift modes — arithmetic operations are excluded.
The output function Xj is read directly from the EV K-map in Fig. 8.41b and is

M,(L/R • £,_, + L/R • fi/ +1), (8.21)

where the quantity (L/R • Bj-\ + L/R • B J+\] represents the shift left or right operation
but only when mode control M\ = 1, as required by the mode control table in Fig. 8.39.
Thus, right shift by one bit occurs when L/R = 1 and left shift by one bit occurs when
L/R = 0. Function Fj represents the 16 possible bitwise logic operations, as in Eq. (8.19),