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368        CHAPTER 8 / ARITHMETIC DEVICES AND ARITHMETIC LOGIC UNITS (ALUs)


                    given in Fig. 8.36.


                                              F = (AQB)C in
                                            C 0ut — Cj n E -j- D
                                                = C in(A O 5) + A 0 B



                    By comparing the result F = (A Q B)Ci n with Eqs. (6.20) for a 1-bit comparator, it becomes
                    evident that C in = eq is the (A = B) output from the next least significant stage.
                       The remaining two operations, (11) and (12), are shift operations that can be considered
                    both arithmetic and logic in nature. For example, operation (11) shifts word A by one bit
                    to the left, which can be interpreted as a x 2 operation, and hence a partial multiplication
                    step. Referring to Section 8.6 and Algorithm 2.10, it is clear that a bit-by-bit left shift is
                    a partial step used to execute the multiplication of two operands. This requires that the
                    7th function bit Fj receive the Cj n from the (/ — l)th stage, and that the C out of the
                    Jth stage be the A input to that stage, for which F = R = C- m = 11002 = 12io and
                    D = A = 0011 2 = 3, 0.
                       There are many other operations possible by the PALU that are not listed in the operation
                    table of Fig. 8.36. As examples, operation (9) can be interpreted as the 1's complement of
                    A according to Algorithm 2.7 as applied to binary, and operation (7) can be considered as a
                    partial product required in the multiplication of two operands. Also, arithmetic operations
                    other than the operations (1), (2), and (3) are possible.
                       There are a total of 16 bitwise logic operations that can be generated by the PALU,
                    but only five are listed in Fig. 8.36. For reference purposes, the 16 logic functions in two
                    operands, A and B, that can be generated by Eqs. (8.17) are summarized by


                                    F =    Finn = F 3AB + F 2AB + F 1AB + F 0AB        (8.19)
                                        i=3


                                                              F                    F
                                                 F 3 F 2 F, F 0      F 3 F 2 F, F 0
                                                 0 0   0 0    0       1 0  0 0    A-B
                                                 0 0   0 1   A-B      1 0  0 1   A0B
                                                 0 0   1 0   A-B      1 0  1 0     B
                                                 0 0 1 1      A       1 0 1 1    A+B
                                                 0 1   0 0   A-B      1 1  0 0    A
                                                 0 1   0 1    B       1 1  0 1   A+B
                                                 0 1   1 0   A0B      1 1  1 0   A + B
                                                 0 1 1 1     A+B      1 1 1 1      1

                                  (a)                             (b)
                    FIGURE 8.38
                    The 16 possible bitwise logic functions for operands A and B according to Eq. (8.19) (a) K-map
                    representation, (b) Tabular representation.
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