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442 CHAPTER 10 / INTRODUCTION TO SYNCHRONOUS STATE MACHINE DESIGN

D+CK
lfCK=1, Q follows D.
.•. Transparent

0 <j>
1 0
PS 1 <! ' " ° 1
0

Characterization of the memory
(a) (b)

FIGURE 10.24
The RET D latch, (a) State diagram for the D latch showing transparency effect when CK = 1. (b)
Excitation table for the basic cell and characterization of the memory.

portions of the clock waveform also minimizes the probability that the transparent effect
can occur. Although this is likely to be true, it is generally recommended that the D latch
not be considered as a viable option when selecting a memory element for FSM design.
Of course, if D can never go active when CK is active, the D latch can be considered as a
viable option for memory in FSM design.
The memory element to be used in the design of the D latch is one or the other of two
basic cells (Fig. 10.18) characterized by the combined excitation table given in Fig. 10.24b.
The plan for design of the D latch is simply to take the information contained in the state
diagram of Fig. 10.24a and in the excitation table in Fig. 10.24b, and bring the two kinds
of information together in the form of next-state K-maps by using the mapping algorithm
given in Section 10.6. When this is done the following information is used for the K-map
entries:

f place 0 • (D + CK) = 0 in Cell 0 of the S K-map }
For 0 —> 0 < _ _ >
(place (/)-(D + CK) = 0(D + CK) in Cell 0 of the R K-map\

( place 1 • (DCK) = DCK in Cell 0 of the S K-map ] J }
place 0 • (DCK) = 0 in Cell 0 of the R K-map
place 0 • (DCK) = 0 in Cell 1 of the S K-map ]
i
( place 1 • (DCK) = DCK in Cell 1 of the R K-map\
[place <j)-(D + CK) = $(D + CK) in Cell 1 of the S K-map]
For 1 -»• 1 { } .
[ place 0 • (DCK) = 0 in Cell 1 of the R K-map J

This results in the next state EV K-maps, minimum next state functions for S and R, and the
logic circuit and symbol all shown in Fig. 10.25. The four null (zero) entries are omitted in
the EV K-maps, leaving only the two essential and two nonessential (don't care) entries for