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11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS 509

in Fig. 11.18b, clearly shows that a static 0-hazard is not possible for the transition 001 — > 101.
This is so because the b—>c branching condition in Fig. 11.14a requires that input T be
active, which is contrary to the requirements indicated by the coupled terms, (Sf ). Thus,
independent of whether or not there is a match between the logic character of the flip-flops
and that of the output logic, no s-hazard is possible in YPQS- Therefore, the addition of
hazard cover is not applicable (NA) as indicated in Fig. 11.15b. Notice that the gate/input
tallies for Y POs and Y SOP are 3/8 and 4/10, respectively, exclusive of inverters and hazard
cover. If hardware cost is the only consideration, the best choice for output logic would be
, as given in Fig. 11.15b.

11 .3.3 Perspective on Static Hazards in the Output Logic of FSMs
Static hazards in the next-state-forming logic are never a problem in synchronous FSMs
simply because the memory flip-flops act as a filtering stage for such logic noise. However,
in the case of s-hazards in the output-forming-logic, the situation is much different. As has
been discussed, a static hazard in the output function of an FSM can cause malfunction of a
next-stage logic device to which the output function is an input. But not every s-hazard may
cross the switching threshold of that next stage device. The problem is that the designer
cannot afford to gamble on that, and instead should take corrective measures such as adding
hazard cover or filtering the output to eliminate the hazard.
Externally initiated s-hazards pose a special dilemma for the designer, since the asym-
metric delay is usually caused by an inverter. The previous discussion suggests that if the
coupled terms require a branching direction opposite to that actually present in the state
diagram, hazard cover may be ignored. In fact, the s-hazard may still be formed if a delay
in the alternative path (not through the inverter) is larger than the inverter. Thus, it may
be desirable to apply the "shotgun approach" to all externally initiated s-hazards in the
output functions. This means that hazard cover would be assigned to all externally coupled
terms regardless or whether they represent a 1 -> 0 change or a 0 — »• 1 change of the cou-
pled external variable as indicated by the state diagram. This action would certainly make
computer-aided corrective action simpler for externally initiated s-hazards.
There is the remote possibility that internally initiated s-hazards may form even if the
logic character of the flip-flops matches that of the output-forming logic. For an s-hazard
to be produced under this condition, a delay larger than that of a basic cell gate would
have to exist in an alternative path so as to effectively reverse the symmetrical inset of the
waveforms in Fig. 10. 1 8. Though the probability that this may happen is low, it is something
of which the designer should be aware.
The following set of guidelines are offered to help eliminate any confusion the foregoing
discussion may have caused and to help establish safe and reliable design practices:

• Add hazard cover for all externally initiated s-hazards in the output logic ex-
pressions as required by the coupled terms. There is one exception to this rule:
If the state in which the externally initiated hazard exists is an extraneous
state (one that neither exists in the state diagram nor serves as a race state),
as was the case in Fig. 11. 9c, no hazard cover is needed and none should be
added.
• If internally initiated s-hazards are present and the goal is to achieve an optimum
design, match the logic character of the flip-flops with that of the output-forming