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510 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS

logic and take no corrective action on these s-hazards. Then, in configuring
a circuit layout try to minimize parasitic effects by minimizing lead lengths
between the flip-flops and output logic. If the logic character of the flip-flops is
unknown, always add hazard cover for all internally coupled terms in the output
logic for which a valid hazardous transition exists. Note that Fig. 11.13 applies
to any PLD in which the internal flip-flops lack Q(L) outputs.
If the outputs of FSM A are the inputs to another FSM B, take caution in assuming
that logic noise (e.g., s-hazards) from FSM A will be filtered by the memory of
FSM B. Whether or not such logic noise will be filtered by the memory of FSM
B depends on many factors, including the type of input conditioning circuits that
exist, the nature of the NS-forming logic, and the character of FSM B itself. If
this information is unknown or questionable, the safest action is to provide clean
output signals from FSM A by using the methods described previously.

11.4 ASYNCHRONOUS INPUTS: RULES AND CAVEATS

A synchronous input is one that is synchronized with clock to the extent that it cannot
change its logic level during a sampling interval (see Fig. 10.53). Any input that does not
meet this requirement is said to be an asynchronous input, defined as follows:

An asynchronous input is one that can change logic levels at any time, particularly
during the sampling interval established by the sampling variable, CK.

As was pointed out in Section 10.11, an input to a synchronous FSM must meet the setup
and hold-time requirements established by clock (the sampling variable) or proper transi-
tions cannot generally be guaranteed. Simply stated, a synchronous FSM may not function
properly if more than one asynchronous input is present. Remember that clock is, by defini-
tion, an asynchronous input. Therefore, CK should be considered to be the only permissible
asynchronous input controlling the branching from a given state.

11.4.1 Rules Associated with Asynchronous Inputs
To reduce the probability for FSM malfunction due to the presence of asynchronous inputs,
the following two rules should be observed:

Rule 1 (Branching Dependency Rule): Avoid branching dependency on more
than one asynchronous input.
Rule 2 (Conditional Output Rule): Do not attempt to generate an output condi-
tional on an asynchronous input.

These two rules are easily justified by discussing the consequences of their violation. For
example, if more than one asynchronous input controls the branching from a given state,
the sequential behavior can become unpredictable, resulting in the malfunction of the FSM.
Furthermore, an output that is conditional on an asynchronous input can, under certain
conditions, be no more than an underdeveloped (runt) pulse that may cause problems in