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514 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS

Metastable
state at
midsupply

Reset
(a) (b) (c)
FIGURE 11.22
Qualitative representations of metastability. (a) Mechanical analogue, (b) FSM metastability mani-
fested as a midsupply state, (c) FSM metastability manifested as an oscillatory state. Ar m = Metastable
exit time.

the rising edge triggering of the FSM. Thus, for each narrow X(L) pulse that is caught,
a stretched X'(H) pulse is picked up by the RET FSM well into the active portion of the
pulse.

11.4.4 Metastability and the Synchronizer
An important function of the synchronizer is to protect an FSM from the effects of metasta-
bility if caused by an input change during the sampling interval of the clock waveform. The
problem is that the synchronizer is itself subject to the effects of metastability caused by data
input changes occurring during its sampling interval. Metastability is a very low-probability
event, but it can happen and can be a potential problem in any system with feedback. Just
as the second law of thermodynamics cannot be violated in attempting to invent a perpet-
ual motion machine, no "fix-it" scheme exists that will reduce to zero the probability that
metastability will occur in a given FSM. But there are synchronizing schemes that can come
close! Before proceeding with the means by which this can be accomplished, it will be
helpful to define metastability in qualitative terms.
Three qualitative representations of metastability are depicted in Fig. 11.22. First is the
mechanical analogue, shown in Fig. 11.22a, featuring a ball or round disk metastably situated
atop a convex surface such that any slight perturbation would send it to one stable state or
another. More appropriate to the needs of FSM design is the electrical representation of the
metastable state that lies somewhere between a set and a reset condition, say at midsupply, as
illustrated in Fig. 11.22b. Here, the time that the FSM spends in the metastable state, denoted
by A/ w , is called the metastable exit time. This is a statistical period of time that cannot
be predicted. The two double-line regions preceding and following the metastable state
represent a stable set or reset condition, one or the other. However, it cannot be predicted
which logic level (set or reset) will emerge following exit from the metastable state. The
oscillatory metastable state illustrated in Fig. 11.22c is also a possibility in some FSMs,
which if exists, could pose a more serious problem for the FSM than a simple midsupply
"hangup." Here again, the logic level (set or reset) following exit from the metastable state