Page 602 - Engineering Digital Design

572 CHAPTER 12 / MODULE AND BIT-SLICE DEVICES

12.3 SYNCHRONOUS BINARY COUNTERS

Synchronous counters form a class of FSMs for which each state code assignment of its state
diagram is taken to be a number in a count sequence. Most simple synchronous counters are
degenerate Moore machines that obey the basic model of Fig. 10.3c, since their only outputs
are the state variables. Other synchronous binary counters are those that have control inputs
and unconditional or conditional outputs, and that adhere to either the Moore or Mealy
model (Fig. 10.4 or 10.5). In any case, such binary counters are classified as modulo-N
counters or as divide-by-N counters, where TV is the number of states of the sequence.
The divide-by-N designation results from the fact that the clock frequency is divided by
N(fcK/N} if taken from the MSB output of the counter. The up/down binary counter of
Figs. 10.57 and 10.58 is classified as a modulo-8 (divide-by-8) bidirectional counter. But as
will soon become evident, it is also a divide-by-8, divide-by-4, or divide-by-2 binary counter
depending on from which output A, B, or C the count is taken, respectively. Any of these
counters can be designed with synchronous or asynchronous parallel load capability, which
means that these counters can begin the synchronous count from the parallel load state.
The state sequence of a synchronous counter need not conform to a regular binary count,
up or down. Synchronous counters can be designed to count in any of the codes defined in
Section 2.10, and in any direction. The most common of these for use in counter design
are the decimal codes, specifically the BCD code. A BCD counter has 10 states and is
accordingly called a decade or divide-by-10 counter. Still, the count sequence does not have
to be binary. Counters can be designed to count in a unit distance code sequence of the type
given in Table 2.12. The most common of these is the Gray code counter that sequences
through states shown in column (2) of Table 2.12, assuming it to be of four bits.
Counters discussed so far are classified as synchronous counters because their flip-
flops are all triggered simultaneously by the clock signal. Counters whose flip-flops are
each triggered by the output of the next LSB stage flip-flop are called ripple counters or
asynchronous counters. Thus, the triggering action of the flip-flops ripples from the LSB
stage flip-flop, where the external clock enters the counter, to the MSB stage flip-flop.
Ripple counters can be designed to up count, or down count, or both. These counters will
be discussed in detail in Section 12.5.
Finally, there is a broad class of synchronous counters that can be designed by using
shift registers of the type discussed in Section 12.2. One such counter, called a ring counter,
sequences through a series of one-hot code states as in column (c) of Table 2.11. Another
counter in this class of counters is called the twisted ring counter (also called the Johnson
or Mobius counter), which sequences through a series of creeping code states as in column
(7) of Table 2.10. Still other counters can be configured with D flip-flops and XOR gates to
form what are called autonomous linear feedback shift register counters or simply ALFSR
counters. ALFSR counters are useful in generating pseudo-random sequences of n-bit
binary numbers, among other uses.
For future reference, the following lists several members of the rather diverse family of
synchronous counters:

Code counters
Binary divide-by-2" counters
Decimal counters (e.g., BCD, XS3 counters)
Gray code counters