Page 623 - Engineering Digital Design

12.4 SHIFT-REGISTER COUNTERS 593

ring counter of Fig. 12.32b can be expanded to an 8-bit, 1-hot ring counter by cascading
two USRs as in Fig. 12.7. But without parallel loading a 1-hot state, the self-correction
logic becomes L = BCDEFGH, a fan-in of 7 for a single gate. Thus, self-correction takes
place within seven clock pulses. Generally, an n-bit ring counter will self-correct within
n — l clock pulses. For such counters and where permitted, the CMOS NOR gate, shown
in Figure 8.46, is preferred since it operates free of fan-in limitations. Alternatively, any bit
pattern can be parallel loaded into an n-bit ring counter and circulated with self-correction.
The advantage of the ring counter is that it provides glitch-free decoded outputs directly
from the flip-flops. This means that one and only one flip-flop is active for each state of the
1-hot sequence. This feature can be very useful for timing sequence generation in control
applications. A down side to the ring counter is that it does not encode its states as efficiently
as binary counters — one flip-flop must be used for each state. Considered next is a type
of counter that can generate twice as many states as the ring counter but with only a minor
increase in overall hardware.

12.4.2 Twisted Ring Counters

A counter that circulates a creeping code, such as that in Column (7) of Table 2.10 in
Subsection 2.10.1, is called a twisted ring counter, or sometimes called a Johnson counter.
The "twist" aspect of this counter is created simply by interposing an inverter in the feedback
line of a standard ring counter or by tapping the feedback line off of the active low output
of the flip-flop. Shown in Fig. 12.33a is the state diagram for a 4-bit twisted ring counter
together with the required branching action for a USR design of this counter. The PS/NS
table for this counter, given in Fig. 12.33b, indicates that a left shift of A generates the next
state for each of the eight states in the sequence. This is shown more vividly in the K-map
of Fig. 12.33c for L, the left-shift serial input of a USR. Notice that all eight extraneous
states are assigned a don't-care symbol.
A USR design of this twisted-ring counter is given in Fig. 12.33d. Notice that it is initial-
ized into the 0000 state, which is one of eight states of the creeping code sequence. Thus,
once initialized the counter will cycle through the creeping code states — that is, unless the
unexpected occurs and the counter is caused to enter an extraneous state. To avoid this po-
tential problem, the counter can be made self-correcting. But to do this requires additional
logic, as was the case for the ring counter of Fig. 12.32b.
The twisted ring counter of Fig. 12.33d can be made self-correcting by making use of
the shift left and parallel load capability of the USR. Shown in Figs. 12.34a and 12.34b
are the K-maps for S 0 and L of the USR. Here, left-shifting of the eight creeping code
states is the same as in Fig. 12.33c, except that state 0 along with states 2, 4, and 6 are
parallel loaded into the 0001 state. Also, the remaining five extraneous states (0101, 1001,
1010, 1011, and 1101) are shifted left an A eventually to states 2, 4, or 6, where they are
subsequently parallel loaded into state 0001. Up to n — 1 = 3 clock pulses are necessary
for the self-correction of this counter shown configured with the USR in Fig. 12.34c.
Twisted ring counters of any size can be designed. By cascading k 4-bit USRs, a twisted
ring counter of 4k bits results that will sequence through 8fc creeping code states. For these
counters the external logic maintains the same form, namely L = A and SQ = QMSB •
QLSB, for self-correction. If self-correction is neglected, then So = Q as in Fig. 12.33d.
The advantage of the twisted ring counter over its cousin, the standard ring counter, is
that 2n states are generated for n flip-flops as opposed to n states for the ring counter.