Page 620 - Engineering Digital Design

590 CHAPTER 12 / MODULE AND BIT-SLICE DEVICES

12.4 SHIFT-REGISTER COUNTERS

Shift registers are normally designed to be operated in one or more of the noncyclic "data"
modes of operation given at the beginning of Section 12.2. However, the flip-flops of a regis-
ter can be configured to operate in a "nondata" cyclic fashion with or without external logic
depending on the desired effect. Registers that are configured to operate in a cyclic fashion
are called shift-register counters. These counters cycle through a sequence of states that gen-
erally conform to one or three types of codes: 1-hot code (Table 2.11), creeping code (Table
2.10), and a pseudo-random code. For future reference, the names of these counters are

Ring counters
Twisted ring (Johnson) counters
Linear feedback shift register (LFSR) counters

An introduction to these counters is provided in the next few subsections.

12.4.1 Ring Counters
A counter that consists of n states and n state variable outputs, such that each output
corresponds to the integers (decimal values) 0 to n — 1 in 1-hot code, is called a ring
counter—the simplest of the shift-register counters. This, of course, assumes that the
counter is initially loaded with a binary word having a single "1." A 10-state 1-hot code
is given in column (c) of Table 2.11 in Subsection 2.10.2. This means that a ring counter
of 10 states would sequence through this 1-hot code in cyclical fashion, but would require
10 flip-flops to accomplish this. In comparison a binary counter having 10 flip-flops would
10
sequence through 2 = 1024 states.
Shown in Fig. 12.30a is the state diagram for a simple 4-bitring counter that will sequence
through a 1-hot code of 4 bits. The present-state/next-state (PS/NS) table for this counter
is given in Fig. 12.30b. A brief inspection of the columns in this table yields the NS logic
expressions, given in Fig. 12.30c, without the need to use K-maps. The nature of the NS
functions requires that the single 1 be circulated around the counter in cyclic fashion.
The logic circuit for this ring counter is shown in Fig. 12.30d. Once initialized into the
0001 state, the "1" will be circulated as illustrated in the state diagram of Fig. 12.30a.
Actually, any bit pattern can be circulated in this fashion. For example, if two 1 's are
initialized into the counter to form an even-parity code, that bit pattern would be circulated
according to the NS functions in Fig. 12.30c.
The ring counter of Fig. 12.30 must be initialized into one of the 1-hot code states. If it is
not initialized, it could power up into any one of the five extraneous subroutines, including
two "hang" states. Even if the counter is properly initialized, there is the possibility that
one of the extraneous subroutines could be entered because of noise or power fluctuation.
To avoid this problem the ring counter can be made self-correcting. To accomplish this, a
missing-state analysis must be made of the 12 don't-care states, as in Fig. 12.3 la, where
five extraneous subroutines are discernible by close inspection of the table. The two hang
states are easily seen to be states 0000 and 1111, since these states branch to themselves.
Correction follows in Fig. 12.3 Ib if it is recognized that all present states must be shifted
left with a 0 except for state 0000, which must be shifted left with a 1. Notice that all 12
extraneous states eventually transit to a 1-hot state, though over varying numbers of clock