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630 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES

of course, don't cares. The composite output K-map in Fig. 13.16c is useful since a state
decoder is to be used to generate all Moore outputs and to reduce the logic necessary for
the Mealy outputs.
Gathering the results so far, the expressions for the serial and parallel load inputs are

L = 1

(13.3)
P B=BC = State 1
PC = BS + C = (State 3) • S + State 5
P D = C = State 5

and for the four outputs

M = (State 1) • V + State 4
N = (State 5) • V
\, (13.4)
P= State 1 '
Q = State 2

where it is understood that the mode control inputs, S\ and So, are to be generated by
8-to-l MUXs and that a state decoder is to be used to produce the State values given
in Eqs. (13.3) and (13.4). It is important for the reader to realize that the State values
in the parallel load and output equations can be read directly from the state diagram. For
example, P B — State 1 since the only parallel load involving state variable B is the branching
01 1 1 -> 0100. Similarly, P c = (State 3) • S + State 5 is due to the parallel load 001 1 -^ 0010
under branching condition S and the unconditional parallel load transition 0101— >• 00 11.
Or, in the case of an output, TV = (State 5) • V results since N is conditional on V in state
0101. Thus, the use of a state decoder can save time and reduce the number of external
gates required for implementation, which, of course, comes at the cost of adding a state
decoder.
Shown in Fig. 13.17 is the FSM of Fig. 13.15a centered around a USR and state decoder
with 8-to-l MUXs used to generate the mode controls, S\ and SQ. Here, the external logic
to the MUXs is the logic contained in the cells of the mode control K-maps, and the parallel
load and output logic follow Eqs. (13.3) and (13.4). An output holding register, triggered
anti-phase to the memory, is necessary since ORGs abound, as can be seen by an inspection
of the state diagram in Fig. 13.15a. Observe that the shifting and parallel load action re-
quired by this FSM presents no problem at the inactive MSB position, A, since that position
accepts a logic 0 in all cases.
The use of the state decoder in Fig. 13.17 is to be considered a design convenience,
and so its presence is arbitrary. A state decoder helps to minimize the parallel load and
output-forming logic and reduces the overall effort in obtaining this logic. In the absence
of a state decoder, one can expect a significant increase in the number of gates required to
implement the parallel load and output logic. For example, without the state decoder, the